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authorRoland Stigge <stigge@antcom.de>2012-06-14 10:16:18 -0400
committerRoland Stigge <stigge@antcom.de>2012-06-14 10:16:18 -0400
commitc70426f1534a7d8e52e478ce67fd4634cc588741 (patch)
tree8ca73976d4ea43c4ecbcc0681b324d0215e1ca3f /arch/arm/boot/dts/lpc32xx.dtsi
parent2c7fa28622d8c00ca41f0362d11c52d9f404f543 (diff)
ARM: LPC32xx: DT conversion of Standard UARTs
This patch switches from static serial driver initialization to devicetree configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled individually via DT. E.g., instead of Kconfig configuration, the phy3250.dts activates UARTs 3 and 5. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi34
1 files changed, 26 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index a9b2a6a22024..acb68171d04d 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -126,24 +126,42 @@
126 reg = <0x2009C000 0x1000>; 126 reg = <0x2009C000 0x1000>;
127 }; 127 };
128 128
129 /* UART5 first since it is the default console, ttyS0 */
130 uart5: serial@40090000 {
131 /* actually, ns16550a w/ 64 byte fifos! */
132 compatible = "nxp,lpc3220-uart";
133 reg = <0x40090000 0x1000>;
134 interrupts = <9 0>;
135 clock-frequency = <13000000>;
136 reg-shift = <2>;
137 status = "disabled";
138 };
139
129 uart3: serial@40080000 { 140 uart3: serial@40080000 {
130 compatible = "nxp,serial"; 141 compatible = "nxp,lpc3220-uart";
131 reg = <0x40080000 0x1000>; 142 reg = <0x40080000 0x1000>;
143 interrupts = <7 0>;
144 clock-frequency = <13000000>;
145 reg-shift = <2>;
146 status = "disabled";
132 }; 147 };
133 148
134 uart4: serial@40088000 { 149 uart4: serial@40088000 {
135 compatible = "nxp,serial"; 150 compatible = "nxp,lpc3220-uart";
136 reg = <0x40088000 0x1000>; 151 reg = <0x40088000 0x1000>;
137 }; 152 interrupts = <8 0>;
138 153 clock-frequency = <13000000>;
139 uart5: serial@40090000 { 154 reg-shift = <2>;
140 compatible = "nxp,serial"; 155 status = "disabled";
141 reg = <0x40090000 0x1000>;
142 }; 156 };
143 157
144 uart6: serial@40098000 { 158 uart6: serial@40098000 {
145 compatible = "nxp,serial"; 159 compatible = "nxp,lpc3220-uart";
146 reg = <0x40098000 0x1000>; 160 reg = <0x40098000 0x1000>;
161 interrupts = <10 0>;
162 clock-frequency = <13000000>;
163 reg-shift = <2>;
164 status = "disabled";
147 }; 165 };
148 166
149 i2c1: i2c@400A0000 { 167 i2c1: i2c@400A0000 {