diff options
| author | Huang Shijie <b32955@freescale.com> | 2013-07-08 05:14:19 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-08-22 11:29:06 -0400 |
| commit | 6eb85f9196e7405264eff977fce36784afe7a5e6 (patch) | |
| tree | 136c7db3082d2ce22dfbfee1d923bc33b90cf59b /arch/arm/boot/dts/imx6sl.dtsi | |
| parent | 38918b72751d58e9edcb30c801253933f03e1d31 (diff) | |
ARM: dts: imx6sl: add "fsl,imx6q-uart" for uart compatible
In order to enable the DMA for some uart port in imx6sl, we add the
"fsl,imx6q-uart" to the uart's compatible property.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6sl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6sl.dtsi | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 9138c67d4961..0a297afce002 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi | |||
| @@ -152,7 +152,8 @@ | |||
| 152 | }; | 152 | }; |
| 153 | 153 | ||
| 154 | uart5: serial@02018000 { | 154 | uart5: serial@02018000 { |
| 155 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 155 | compatible = "fsl,imx6sl-uart", |
| 156 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 156 | reg = <0x02018000 0x4000>; | 157 | reg = <0x02018000 0x4000>; |
| 157 | interrupts = <0 30 0x04>; | 158 | interrupts = <0 30 0x04>; |
| 158 | clocks = <&clks IMX6SL_CLK_UART>, | 159 | clocks = <&clks IMX6SL_CLK_UART>, |
| @@ -162,7 +163,8 @@ | |||
| 162 | }; | 163 | }; |
| 163 | 164 | ||
| 164 | uart1: serial@02020000 { | 165 | uart1: serial@02020000 { |
| 165 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 166 | compatible = "fsl,imx6sl-uart", |
| 167 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 166 | reg = <0x02020000 0x4000>; | 168 | reg = <0x02020000 0x4000>; |
| 167 | interrupts = <0 26 0x04>; | 169 | interrupts = <0 26 0x04>; |
| 168 | clocks = <&clks IMX6SL_CLK_UART>, | 170 | clocks = <&clks IMX6SL_CLK_UART>, |
| @@ -172,7 +174,8 @@ | |||
| 172 | }; | 174 | }; |
| 173 | 175 | ||
| 174 | uart2: serial@02024000 { | 176 | uart2: serial@02024000 { |
| 175 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 177 | compatible = "fsl,imx6sl-uart", |
| 178 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 176 | reg = <0x02024000 0x4000>; | 179 | reg = <0x02024000 0x4000>; |
| 177 | interrupts = <0 27 0x04>; | 180 | interrupts = <0 27 0x04>; |
| 178 | clocks = <&clks IMX6SL_CLK_UART>, | 181 | clocks = <&clks IMX6SL_CLK_UART>, |
| @@ -209,7 +212,8 @@ | |||
| 209 | }; | 212 | }; |
| 210 | 213 | ||
| 211 | uart3: serial@02034000 { | 214 | uart3: serial@02034000 { |
| 212 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 215 | compatible = "fsl,imx6sl-uart", |
| 216 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 213 | reg = <0x02034000 0x4000>; | 217 | reg = <0x02034000 0x4000>; |
| 214 | interrupts = <0 28 0x04>; | 218 | interrupts = <0 28 0x04>; |
| 215 | clocks = <&clks IMX6SL_CLK_UART>, | 219 | clocks = <&clks IMX6SL_CLK_UART>, |
| @@ -219,7 +223,8 @@ | |||
| 219 | }; | 223 | }; |
| 220 | 224 | ||
| 221 | uart4: serial@02038000 { | 225 | uart4: serial@02038000 { |
| 222 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | 226 | compatible = "fsl,imx6sl-uart", |
| 227 | "fsl,imx6q-uart", "fsl,imx21-uart"; | ||
| 223 | reg = <0x02038000 0x4000>; | 228 | reg = <0x02038000 0x4000>; |
| 224 | interrupts = <0 29 0x04>; | 229 | interrupts = <0 29 0x04>; |
| 225 | clocks = <&clks IMX6SL_CLK_UART>, | 230 | clocks = <&clks IMX6SL_CLK_UART>, |