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authorTim Harvey <tharvey@gateworks.com>2014-09-09 02:07:30 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-09-15 22:27:20 -0400
commitb5f37b76053afe8863ce9a753903932eb542eca9 (patch)
tree1bbc5345afd12d6e3771312c7b826f10e8ffeb2e /arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
parent73e005c111bc3f77ca3793d465539a11e7604c71 (diff)
ARM: dts: imx: ventana: cleanup pinctrl groups
Follow the conventions for pinctrl: - grouping pinctrl in logical alphabatized groups - remove any pinctrl not being used by a driver or needed by user - move iomuxc to bottom of file for readability Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-gw53xx.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi224
1 files changed, 115 insertions, 109 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index e6e298bb7576..cade1bdc97e9 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -37,6 +37,8 @@
37 37
38 leds { 38 leds {
39 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
40 42
41 led0: user1 { 43 led0: user1 {
42 label = "user1"; 44 label = "user1";
@@ -64,6 +66,8 @@
64 66
65 pps { 67 pps {
66 compatible = "pps-gpio"; 68 compatible = "pps-gpio";
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
67 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 71 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
68 status = "okay"; 72 status = "okay";
69 }; 73 };
@@ -240,41 +244,101 @@
240 }; 244 };
241}; 245};
242 246
243&iomuxc { 247&ldb {
244 pinctrl-names = "default"; 248 status = "okay";
245 pinctrl-0 = <&pinctrl_hog>;
246 249
247 imx6qdl-gw53xx { 250 lvds-channel@1 {
248 pinctrl_hog: hoggrp { 251 fsl,data-mapping = "spwg";
249 fsl,pins = < 252 fsl,data-width = <18>;
250 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* PCIE6EXP_DIO0 */ 253 status = "okay";
251 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* PCIE6EXP_DIO1 */ 254
252 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */ 255 display-timings {
253 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_SHDN */ 256 native-mode = <&timing0>;
254 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */ 257 timing0: hsd100pxn1 {
255 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */ 258 clock-frequency = <65000000>;
256 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */ 259 hactive = <1024>;
257 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ 260 vactive = <768>;
258 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ 261 hback-porch = <220>;
259 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 262 hfront-porch = <40>;
260 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* HUB_RST# */ 263 vback-porch = <21>;
261 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIE_WDIS# */ 264 vfront-porch = <7>;
262 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0001b0b0 /* ACCEL_IRQ# */ 265 hsync-len = <60>;
263 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */ 266 vsync-len = <10>;
264 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0001b0b0 /* USBOTG_OC# */ 267 };
265 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */
266 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */
267 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* TOUCH_IRQ# */
268 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_DET# */
269 >;
270 }; 268 };
269 };
270};
271
272&pcie {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_pcie>;
275 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
276 status = "okay";
277
278 eth1: sky2@8 { /* MAC/PHY on bus 8 */
279 compatible = "marvell,sky2";
280 };
281};
282
283&pwm4 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_pwm4>;
286 status = "okay";
287};
288
289&ssi1 {
290 fsl,mode = "i2s-slave";
291 status = "okay";
292};
271 293
294&uart1 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_uart1>;
297 status = "okay";
298};
299
300&uart2 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_uart2>;
303 status = "okay";
304};
305
306&uart5 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart5>;
309 status = "okay";
310};
311
312&usbotg {
313 vbus-supply = <&reg_usb_otg_vbus>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usbotg>;
316 disable-over-current;
317 status = "okay";
318};
319
320&usbh1 {
321 vbus-supply = <&reg_usb_h1_vbus>;
322 status = "okay";
323};
324
325&usdhc3 {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_usdhc3>;
328 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
329 vmmc-supply = <&reg_3p3v>;
330 status = "okay";
331};
332
333&iomuxc {
334 imx6qdl-gw53xx {
272 pinctrl_audmux: audmuxgrp { 335 pinctrl_audmux: audmuxgrp {
273 fsl,pins = < 336 fsl,pins = <
274 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 337 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
275 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 338 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
276 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 339 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
277 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 340 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
341 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
278 >; 342 >;
279 }; 343 };
280 344
@@ -303,6 +367,15 @@
303 fsl,pins = < 367 fsl,pins = <
304 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 368 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
305 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 369 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
370 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
371 >;
372 };
373
374 pinctrl_gpio_leds: gpioledsgrp {
375 fsl,pins = <
376 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
377 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
378 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
306 >; 379 >;
307 }; 380 };
308 381
@@ -348,6 +421,19 @@
348 >; 421 >;
349 }; 422 };
350 423
424 pinctrl_pcie: pciegrp {
425 fsl,pins = <
426 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
427 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
428 >;
429 };
430
431 pinctrl_pps: ppsgrp {
432 fsl,pins = <
433 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
434 >;
435 };
436
351 pinctrl_pwm4: pwm4grp { 437 pinctrl_pwm4: pwm4grp {
352 fsl,pins = < 438 fsl,pins = <
353 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 439 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
@@ -378,6 +464,8 @@
378 pinctrl_usbotg: usbotggrp { 464 pinctrl_usbotg: usbotggrp {
379 fsl,pins = < 465 fsl,pins = <
380 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 466 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
467 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
468 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
381 >; 469 >;
382 }; 470 };
383 471
@@ -389,90 +477,8 @@
389 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 477 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
390 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 478 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
391 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 479 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
480 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
392 >; 481 >;
393 }; 482 };
394 }; 483 };
395}; 484};
396
397&ldb {
398 status = "okay";
399
400 lvds-channel@1 {
401 fsl,data-mapping = "spwg";
402 fsl,data-width = <18>;
403 status = "okay";
404
405 display-timings {
406 native-mode = <&timing0>;
407 timing0: hsd100pxn1 {
408 clock-frequency = <65000000>;
409 hactive = <1024>;
410 vactive = <768>;
411 hback-porch = <220>;
412 hfront-porch = <40>;
413 vback-porch = <21>;
414 vfront-porch = <7>;
415 hsync-len = <60>;
416 vsync-len = <10>;
417 };
418 };
419 };
420};
421
422&pcie {
423 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
424 status = "okay";
425
426 eth1: sky2@8 { /* MAC/PHY on bus 8 */
427 compatible = "marvell,sky2";
428 };
429};
430
431&pwm4 {
432 pinctrl-names = "default";
433 pinctrl-0 = <&pinctrl_pwm4>;
434 status = "okay";
435};
436
437&ssi1 {
438 status = "okay";
439};
440
441&uart1 {
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_uart1>;
444 status = "okay";
445};
446
447&uart2 {
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_uart2>;
450 status = "okay";
451};
452
453&uart5 {
454 pinctrl-names = "default";
455 pinctrl-0 = <&pinctrl_uart5>;
456 status = "okay";
457};
458
459&usbotg {
460 vbus-supply = <&reg_usb_otg_vbus>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_usbotg>;
463 disable-over-current;
464 status = "okay";
465};
466
467&usbh1 {
468 vbus-supply = <&reg_usb_h1_vbus>;
469 status = "okay";
470};
471
472&usdhc3 {
473 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_usdhc3>;
475 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
476 vmmc-supply = <&reg_3p3v>;
477 status = "okay";
478};
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 12:55:22 -0400