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authorShawn Guo <shawn.guo@linaro.org>2011-09-06 01:53:26 -0400
committerArnd Bergmann <arnd@arndb.de>2011-10-31 09:26:20 -0400
commit7d740f87fd0741c00231a4b13074660d526d5630 (patch)
treeaa65429bf9d8c1e7f89a9a7036338cad1eaf5f3d /arch/arm/boot/dts/imx6q.dtsi
parentccfa8b21f20099b950b4f2f75d2330fb149a2012 (diff)
arm/imx6q: add device tree source
It adds device tree source and documentation for imx6q platform. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi575
1 files changed, 575 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
new file mode 100644
index 000000000000..7dda599558cc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -0,0 +1,575 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 serial3 = &uart3;
21 serial4 = &uart4;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 compatible = "arm,cortex-a9";
30 reg = <0>;
31 next-level-cache = <&L2>;
32 };
33
34 cpu@1 {
35 compatible = "arm,cortex-a9";
36 reg = <1>;
37 next-level-cache = <&L2>;
38 };
39
40 cpu@2 {
41 compatible = "arm,cortex-a9";
42 reg = <2>;
43 next-level-cache = <&L2>;
44 };
45
46 cpu@3 {
47 compatible = "arm,cortex-a9";
48 reg = <3>;
49 next-level-cache = <&L2>;
50 };
51 };
52
53 intc: interrupt-controller@00a01000 {
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58 interrupt-controller;
59 reg = <0x00a01000 0x1000>,
60 <0x00a00100 0x100>;
61 };
62
63 clocks {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ckil {
68 compatible = "fsl,imx-ckil", "fixed-clock";
69 clock-frequency = <32768>;
70 };
71
72 ckih1 {
73 compatible = "fsl,imx-ckih1", "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 osc {
78 compatible = "fsl,imx-osc", "fixed-clock";
79 clock-frequency = <24000000>;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&intc>;
88 ranges;
89
90 timer@00a00600 {
91 compatible = "arm,smp-twd";
92 reg = <0x00a00600 0x100>;
93 interrupts = <1 13 0xf4>;
94 };
95
96 L2: l2-cache@00a02000 {
97 compatible = "arm,pl310-cache";
98 reg = <0x00a02000 0x1000>;
99 interrupts = <0 92 0x04>;
100 cache-unified;
101 cache-level = <2>;
102 };
103
104 aips-bus@02000000 { /* AIPS1 */
105 compatible = "fsl,aips-bus", "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0x02000000 0x100000>;
109 ranges;
110
111 spba-bus@02000000 {
112 compatible = "fsl,spba-bus", "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x02000000 0x40000>;
116 ranges;
117
118 spdif@02004000 {
119 reg = <0x02004000 0x4000>;
120 interrupts = <0 52 0x04>;
121 };
122
123 ecspi@02008000 { /* eCSPI1 */
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
127 reg = <0x02008000 0x4000>;
128 interrupts = <0 31 0x04>;
129 status = "disabled";
130 };
131
132 ecspi@0200c000 { /* eCSPI2 */
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
136 reg = <0x0200c000 0x4000>;
137 interrupts = <0 32 0x04>;
138 status = "disabled";
139 };
140
141 ecspi@02010000 { /* eCSPI3 */
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
145 reg = <0x02010000 0x4000>;
146 interrupts = <0 33 0x04>;
147 status = "disabled";
148 };
149
150 ecspi@02014000 { /* eCSPI4 */
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
154 reg = <0x02014000 0x4000>;
155 interrupts = <0 34 0x04>;
156 status = "disabled";
157 };
158
159 ecspi@02018000 { /* eCSPI5 */
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
163 reg = <0x02018000 0x4000>;
164 interrupts = <0 35 0x04>;
165 status = "disabled";
166 };
167
168 uart0: uart@02020000 { /* UART1 */
169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>;
172 status = "disabled";
173 };
174
175 esai@02024000 {
176 reg = <0x02024000 0x4000>;
177 interrupts = <0 51 0x04>;
178 };
179
180 ssi@02028000 { /* SSI1 */
181 reg = <0x02028000 0x4000>;
182 interrupts = <0 46 0x04>;
183 };
184
185 ssi@0202c000 { /* SSI2 */
186 reg = <0x0202c000 0x4000>;
187 interrupts = <0 47 0x04>;
188 };
189
190 ssi@02030000 { /* SSI3 */
191 reg = <0x02030000 0x4000>;
192 interrupts = <0 48 0x04>;
193 };
194
195 asrc@02034000 {
196 reg = <0x02034000 0x4000>;
197 interrupts = <0 50 0x04>;
198 };
199
200 spba@0203c000 {
201 reg = <0x0203c000 0x4000>;
202 };
203 };
204
205 vpu@02040000 {
206 reg = <0x02040000 0x3c000>;
207 interrupts = <0 3 0x04 0 12 0x04>;
208 };
209
210 aipstz@0207c000 { /* AIPSTZ1 */
211 reg = <0x0207c000 0x4000>;
212 };
213
214 pwm@02080000 { /* PWM1 */
215 reg = <0x02080000 0x4000>;
216 interrupts = <0 83 0x04>;
217 };
218
219 pwm@02084000 { /* PWM2 */
220 reg = <0x02084000 0x4000>;
221 interrupts = <0 84 0x04>;
222 };
223
224 pwm@02088000 { /* PWM3 */
225 reg = <0x02088000 0x4000>;
226 interrupts = <0 85 0x04>;
227 };
228
229 pwm@0208c000 { /* PWM4 */
230 reg = <0x0208c000 0x4000>;
231 interrupts = <0 86 0x04>;
232 };
233
234 flexcan@02090000 { /* CAN1 */
235 reg = <0x02090000 0x4000>;
236 interrupts = <0 110 0x04>;
237 };
238
239 flexcan@02094000 { /* CAN2 */
240 reg = <0x02094000 0x4000>;
241 interrupts = <0 111 0x04>;
242 };
243
244 gpt@02098000 {
245 compatible = "fsl,imx6q-gpt";
246 reg = <0x02098000 0x4000>;
247 interrupts = <0 55 0x04>;
248 };
249
250 gpio0: gpio@0209c000 { /* GPIO1 */
251 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
252 reg = <0x0209c000 0x4000>;
253 interrupts = <0 66 0x04 0 67 0x04>;
254 gpio-controller;
255 #gpio-cells = <2>;
256 interrupt-controller;
257 #interrupt-cells = <1>;
258 };
259
260 gpio1: gpio@020a0000 { /* GPIO2 */
261 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
262 reg = <0x020a0000 0x4000>;
263 interrupts = <0 68 0x04 0 69 0x04>;
264 gpio-controller;
265 #gpio-cells = <2>;
266 interrupt-controller;
267 #interrupt-cells = <1>;
268 };
269
270 gpio2: gpio@020a4000 { /* GPIO3 */
271 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
272 reg = <0x020a4000 0x4000>;
273 interrupts = <0 70 0x04 0 71 0x04>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
277 #interrupt-cells = <1>;
278 };
279
280 gpio3: gpio@020a8000 { /* GPIO4 */
281 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
282 reg = <0x020a8000 0x4000>;
283 interrupts = <0 72 0x04 0 73 0x04>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <1>;
288 };
289
290 gpio4: gpio@020ac000 { /* GPIO5 */
291 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
292 reg = <0x020ac000 0x4000>;
293 interrupts = <0 74 0x04 0 75 0x04>;
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <1>;
298 };
299
300 gpio5: gpio@020b0000 { /* GPIO6 */
301 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
302 reg = <0x020b0000 0x4000>;
303 interrupts = <0 76 0x04 0 77 0x04>;
304 gpio-controller;
305 #gpio-cells = <2>;
306 interrupt-controller;
307 #interrupt-cells = <1>;
308 };
309
310 gpio6: gpio@020b4000 { /* GPIO7 */
311 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
312 reg = <0x020b4000 0x4000>;
313 interrupts = <0 78 0x04 0 79 0x04>;
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <1>;
318 };
319
320 kpp@020b8000 {
321 reg = <0x020b8000 0x4000>;
322 interrupts = <0 82 0x04>;
323 };
324
325 wdog@020bc000 { /* WDOG1 */
326 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
327 reg = <0x020bc000 0x4000>;
328 interrupts = <0 80 0x04>;
329 status = "disabled";
330 };
331
332 wdog@020c0000 { /* WDOG2 */
333 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
334 reg = <0x020c0000 0x4000>;
335 interrupts = <0 81 0x04>;
336 status = "disabled";
337 };
338
339 ccm@020c4000 {
340 compatible = "fsl,imx6q-ccm";
341 reg = <0x020c4000 0x4000>;
342 interrupts = <0 87 0x04 0 88 0x04>;
343 };
344
345 anatop@020c8000 {
346 compatible = "fsl,imx6q-anatop";
347 reg = <0x020c8000 0x1000>;
348 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
349 };
350
351 usbphy@020c9000 { /* USBPHY1 */
352 reg = <0x020c9000 0x1000>;
353 interrupts = <0 44 0x04>;
354 };
355
356 usbphy@020ca000 { /* USBPHY2 */
357 reg = <0x020ca000 0x1000>;
358 interrupts = <0 45 0x04>;
359 };
360
361 snvs@020cc000 {
362 reg = <0x020cc000 0x4000>;
363 interrupts = <0 19 0x04 0 20 0x04>;
364 };
365
366 epit@020d0000 { /* EPIT1 */
367 reg = <0x020d0000 0x4000>;
368 interrupts = <0 56 0x04>;
369 };
370
371 epit@020d4000 { /* EPIT2 */
372 reg = <0x020d4000 0x4000>;
373 interrupts = <0 57 0x04>;
374 };
375
376 src@020d8000 {
377 compatible = "fsl,imx6q-src";
378 reg = <0x020d8000 0x4000>;
379 interrupts = <0 91 0x04 0 96 0x04>;
380 };
381
382 gpc@020dc000 {
383 compatible = "fsl,imx6q-gpc";
384 reg = <0x020dc000 0x4000>;
385 interrupts = <0 89 0x04 0 90 0x04>;
386 };
387
388 iomuxc@020e0000 {
389 reg = <0x020e0000 0x4000>;
390 };
391
392 dcic@020e4000 { /* DCIC1 */
393 reg = <0x020e4000 0x4000>;
394 interrupts = <0 124 0x04>;
395 };
396
397 dcic@020e8000 { /* DCIC2 */
398 reg = <0x020e8000 0x4000>;
399 interrupts = <0 125 0x04>;
400 };
401
402 sdma@020ec000 {
403 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
404 reg = <0x020ec000 0x4000>;
405 interrupts = <0 2 0x04>;
406 };
407 };
408
409 aips-bus@02100000 { /* AIPS2 */
410 compatible = "fsl,aips-bus", "simple-bus";
411 #address-cells = <1>;
412 #size-cells = <1>;
413 reg = <0x02100000 0x100000>;
414 ranges;
415
416 caam@02100000 {
417 reg = <0x02100000 0x40000>;
418 interrupts = <0 105 0x04 0 106 0x04>;
419 };
420
421 aipstz@0217c000 { /* AIPSTZ2 */
422 reg = <0x0217c000 0x4000>;
423 };
424
425 enet@02188000 {
426 compatible = "fsl,imx6q-fec";
427 reg = <0x02188000 0x4000>;
428 interrupts = <0 118 0x04 0 119 0x04>;
429 status = "disabled";
430 };
431
432 mlb@0218c000 {
433 reg = <0x0218c000 0x4000>;
434 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
435 };
436
437 usdhc@02190000 { /* uSDHC1 */
438 compatible = "fsl,imx6q-usdhc";
439 reg = <0x02190000 0x4000>;
440 interrupts = <0 22 0x04>;
441 status = "disabled";
442 };
443
444 usdhc@02194000 { /* uSDHC2 */
445 compatible = "fsl,imx6q-usdhc";
446 reg = <0x02194000 0x4000>;
447 interrupts = <0 23 0x04>;
448 status = "disabled";
449 };
450
451 usdhc@02198000 { /* uSDHC3 */
452 compatible = "fsl,imx6q-usdhc";
453 reg = <0x02198000 0x4000>;
454 interrupts = <0 24 0x04>;
455 status = "disabled";
456 };
457
458 usdhc@0219c000 { /* uSDHC4 */
459 compatible = "fsl,imx6q-usdhc";
460 reg = <0x0219c000 0x4000>;
461 interrupts = <0 25 0x04>;
462 status = "disabled";
463 };
464
465 i2c@021a0000 { /* I2C1 */
466 #address-cells = <1>;
467 #size-cells = <0>;
468 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
469 reg = <0x021a0000 0x4000>;
470 interrupts = <0 36 0x04>;
471 status = "disabled";
472 };
473
474 i2c@021a4000 { /* I2C2 */
475 #address-cells = <1>;
476 #size-cells = <0>;
477 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
478 reg = <0x021a4000 0x4000>;
479 interrupts = <0 37 0x04>;
480 status = "disabled";
481 };
482
483 i2c@021a8000 { /* I2C3 */
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
487 reg = <0x021a8000 0x4000>;
488 interrupts = <0 38 0x04>;
489 status = "disabled";
490 };
491
492 romcp@021ac000 {
493 reg = <0x021ac000 0x4000>;
494 };
495
496 mmdc@021b0000 { /* MMDC0 */
497 compatible = "fsl,imx6q-mmdc";
498 reg = <0x021b0000 0x4000>;
499 };
500
501 mmdc@021b4000 { /* MMDC1 */
502 reg = <0x021b4000 0x4000>;
503 };
504
505 weim@021b8000 {
506 reg = <0x021b8000 0x4000>;
507 interrupts = <0 14 0x04>;
508 };
509
510 ocotp@021bc000 {
511 reg = <0x021bc000 0x4000>;
512 };
513
514 ocotp@021c0000 {
515 reg = <0x021c0000 0x4000>;
516 interrupts = <0 21 0x04>;
517 };
518
519 tzasc@021d0000 { /* TZASC1 */
520 reg = <0x021d0000 0x4000>;
521 interrupts = <0 108 0x04>;
522 };
523
524 tzasc@021d4000 { /* TZASC2 */
525 reg = <0x021d4000 0x4000>;
526 interrupts = <0 109 0x04>;
527 };
528
529 audmux@021d8000 {
530 reg = <0x021d8000 0x4000>;
531 };
532
533 mipi@021dc000 { /* MIPI-CSI */
534 reg = <0x021dc000 0x4000>;
535 };
536
537 mipi@021e0000 { /* MIPI-DSI */
538 reg = <0x021e0000 0x4000>;
539 };
540
541 vdoa@021e4000 {
542 reg = <0x021e4000 0x4000>;
543 interrupts = <0 18 0x04>;
544 };
545
546 uart1: uart@021e8000 { /* UART2 */
547 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
548 reg = <0x021e8000 0x4000>;
549 interrupts = <0 27 0x04>;
550 status = "disabled";
551 };
552
553 uart2: uart@021ec000 { /* UART3 */
554 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
555 reg = <0x021ec000 0x4000>;
556 interrupts = <0 28 0x04>;
557 status = "disabled";
558 };
559
560 uart3: uart@021f0000 { /* UART4 */
561 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
562 reg = <0x021f0000 0x4000>;
563 interrupts = <0 29 0x04>;
564 status = "disabled";
565 };
566
567 uart4: uart@021f4000 { /* UART5 */
568 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
569 reg = <0x021f4000 0x4000>;
570 interrupts = <0 30 0x04>;
571 status = "disabled";
572 };
573 };
574 };
575};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 17:53:58 -0500