diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2012-08-11 10:06:26 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2012-09-11 04:26:48 -0400 |
| commit | 497ae1747b8c52fde4ab7e9987326ca43886b652 (patch) | |
| tree | 0e70b52b9e682a8217fef17a988ceacd95a47e83 /arch/arm/boot/dts/imx6q.dtsi | |
| parent | 9e3c00665d915c4f5645d43aec5a943b5eee55de (diff) | |
ARM: dts: imx6q-sabresd: add pinctrl settings
Add pinctrl settings for existing devices in imx6q-sabresd.dts.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index f6c99f722f4c..1d07be2530b5 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -609,6 +609,15 @@ | |||
| 609 | }; | 609 | }; |
| 610 | }; | 610 | }; |
| 611 | 611 | ||
| 612 | uart1 { | ||
| 613 | pinctrl_uart1_1: uart1grp-1 { | ||
| 614 | fsl,pins = < | ||
| 615 | 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ | ||
| 616 | 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ | ||
| 617 | >; | ||
| 618 | }; | ||
| 619 | }; | ||
| 620 | |||
| 612 | uart2 { | 621 | uart2 { |
| 613 | pinctrl_uart2_1: uart2grp-1 { | 622 | pinctrl_uart2_1: uart2grp-1 { |
| 614 | fsl,pins = < | 623 | fsl,pins = < |
| @@ -627,6 +636,23 @@ | |||
| 627 | }; | 636 | }; |
| 628 | }; | 637 | }; |
| 629 | 638 | ||
| 639 | usdhc2 { | ||
| 640 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 641 | fsl,pins = < | ||
| 642 | 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ | ||
| 643 | 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ | ||
| 644 | 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ | ||
| 645 | 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ | ||
| 646 | 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ | ||
| 647 | 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ | ||
| 648 | 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ | ||
| 649 | 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ | ||
| 650 | 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ | ||
| 651 | 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ | ||
| 652 | >; | ||
| 653 | }; | ||
| 654 | }; | ||
| 655 | |||
| 630 | usdhc3 { | 656 | usdhc3 { |
| 631 | pinctrl_usdhc3_1: usdhc3grp-1 { | 657 | pinctrl_usdhc3_1: usdhc3grp-1 { |
| 632 | fsl,pins = < | 658 | fsl,pins = < |