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authorShawn Guo <shawn.guo@linaro.org>2013-02-19 21:32:52 -0500
committerShawn Guo <shawn.guo@linaro.org>2013-04-09 10:52:50 -0400
commite16415313c9b00b1adc313e85c2c8a81febe0b98 (patch)
treeb1e804b1bb647f3984036d9f9befbe53023bc519 /arch/arm/boot/dts/imx6q.dtsi
parent36dffd8f49bc1364998db81bee739ea4574d88f7 (diff)
pinctrl: imx: move hard-coding data into device tree
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi221
1 files changed, 111 insertions, 110 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 0d5a7178214f..095333b5b50f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -9,6 +9,7 @@
9 */ 9 */
10 10
11#include "imx6qdl.dtsi" 11#include "imx6qdl.dtsi"
12#include "imx6q-pinfunc.h"
12 13
13/ { 14/ {
14 cpus { 15 cpus {
@@ -78,10 +79,10 @@
78 audmux { 79 audmux {
79 pinctrl_audmux_1: audmux-1 { 80 pinctrl_audmux_1: audmux-1 {
80 fsl,pins = < 81 fsl,pins = <
81 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ 82 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
82 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ 83 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
83 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ 84 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
84 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ 85 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
85 >; 86 >;
86 }; 87 };
87 }; 88 };
@@ -89,9 +90,9 @@
89 ecspi1 { 90 ecspi1 {
90 pinctrl_ecspi1_1: ecspi1grp-1 { 91 pinctrl_ecspi1_1: ecspi1grp-1 {
91 fsl,pins = < 92 fsl,pins = <
92 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ 93 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
93 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ 94 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
94 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ 95 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
95 >; 96 >;
96 }; 97 };
97 }; 98 };
@@ -99,42 +100,42 @@
99 enet { 100 enet {
100 pinctrl_enet_1: enetgrp-1 { 101 pinctrl_enet_1: enetgrp-1 {
101 fsl,pins = < 102 fsl,pins = <
102 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ 103 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
103 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ 104 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
104 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ 105 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
105 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ 106 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
106 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ 107 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
107 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ 108 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
108 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ 109 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
109 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ 110 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
110 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ 111 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
111 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ 112 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
112 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ 113 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
113 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ 114 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
114 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ 115 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
115 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ 116 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
116 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ 117 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
117 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ 118 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
118 >; 119 >;
119 }; 120 };
120 121
121 pinctrl_enet_2: enetgrp-2 { 122 pinctrl_enet_2: enetgrp-2 {
122 fsl,pins = < 123 fsl,pins = <
123 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ 124 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
124 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ 125 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
125 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ 126 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
126 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ 127 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
127 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ 128 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
128 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ 129 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
129 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ 130 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
130 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ 131 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
131 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ 132 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
132 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ 133 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
133 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ 134 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
134 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ 135 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
135 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ 136 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
136 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ 137 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
137 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ 138 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
138 >; 139 >;
139 }; 140 };
140 }; 141 };
@@ -142,25 +143,25 @@
142 gpmi-nand { 143 gpmi-nand {
143 pinctrl_gpmi_nand_1: gpmi-nand-1 { 144 pinctrl_gpmi_nand_1: gpmi-nand-1 {
144 fsl,pins = < 145 fsl,pins = <
145 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ 146 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
146 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ 147 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
147 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ 148 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
148 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ 149 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
149 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ 150 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
150 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ 151 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
151 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ 152 MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
152 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ 153 MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
153 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ 154 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
154 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ 155 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
155 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ 156 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
156 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ 157 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
157 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ 158 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
158 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ 159 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
159 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ 160 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
160 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ 161 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
161 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ 162 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
162 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ 163 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
163 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ 164 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
164 >; 165 >;
165 }; 166 };
166 }; 167 };
@@ -168,8 +169,8 @@
168 i2c1 { 169 i2c1 {
169 pinctrl_i2c1_1: i2c1grp-1 { 170 pinctrl_i2c1_1: i2c1grp-1 {
170 fsl,pins = < 171 fsl,pins = <
171 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ 172 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
172 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ 173 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
173 >; 174 >;
174 }; 175 };
175 }; 176 };
@@ -177,8 +178,8 @@
177 uart1 { 178 uart1 {
178 pinctrl_uart1_1: uart1grp-1 { 179 pinctrl_uart1_1: uart1grp-1 {
179 fsl,pins = < 180 fsl,pins = <
180 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ 181 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
181 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ 182 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
182 >; 183 >;
183 }; 184 };
184 }; 185 };
@@ -186,8 +187,8 @@
186 uart2 { 187 uart2 {
187 pinctrl_uart2_1: uart2grp-1 { 188 pinctrl_uart2_1: uart2grp-1 {
188 fsl,pins = < 189 fsl,pins = <
189 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ 190 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
190 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ 191 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
191 >; 192 >;
192 }; 193 };
193 }; 194 };
@@ -195,8 +196,8 @@
195 uart4 { 196 uart4 {
196 pinctrl_uart4_1: uart4grp-1 { 197 pinctrl_uart4_1: uart4grp-1 {
197 fsl,pins = < 198 fsl,pins = <
198 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ 199 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
199 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ 200 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
200 >; 201 >;
201 }; 202 };
202 }; 203 };
@@ -204,13 +205,13 @@
204 usbotg { 205 usbotg {
205 pinctrl_usbotg_1: usbotggrp-1 { 206 pinctrl_usbotg_1: usbotggrp-1 {
206 fsl,pins = < 207 fsl,pins = <
207 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ 208 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
208 >; 209 >;
209 }; 210 };
210 211
211 pinctrl_usbotg_2: usbotggrp-2 { 212 pinctrl_usbotg_2: usbotggrp-2 {
212 fsl,pins = < 213 fsl,pins = <
213 1591 0x17059 /* MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID */ 214 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
214 >; 215 >;
215 }; 216 };
216 }; 217 };
@@ -218,16 +219,16 @@
218 usdhc2 { 219 usdhc2 {
219 pinctrl_usdhc2_1: usdhc2grp-1 { 220 pinctrl_usdhc2_1: usdhc2grp-1 {
220 fsl,pins = < 221 fsl,pins = <
221 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ 222 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
222 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ 223 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
223 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ 224 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
224 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ 225 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
225 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ 226 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
226 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ 227 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
227 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ 228 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
228 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ 229 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
229 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ 230 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
230 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ 231 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
231 >; 232 >;
232 }; 233 };
233 }; 234 };
@@ -235,27 +236,27 @@
235 usdhc3 { 236 usdhc3 {
236 pinctrl_usdhc3_1: usdhc3grp-1 { 237 pinctrl_usdhc3_1: usdhc3grp-1 {
237 fsl,pins = < 238 fsl,pins = <
238 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ 239 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
239 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ 240 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
240 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ 241 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
241 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ 242 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
242 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ 243 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
243 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ 244 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
244 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ 245 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
245 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ 246 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
246 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ 247 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
247 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ 248 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
248 >; 249 >;
249 }; 250 };
250 251
251 pinctrl_usdhc3_2: usdhc3grp-2 { 252 pinctrl_usdhc3_2: usdhc3grp-2 {
252 fsl,pins = < 253 fsl,pins = <
253 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ 254 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
254 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ 255 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
255 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ 256 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
256 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ 257 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
257 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ 258 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
258 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ 259 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
259 >; 260 >;
260 }; 261 };
261 }; 262 };
@@ -263,27 +264,27 @@
263 usdhc4 { 264 usdhc4 {
264 pinctrl_usdhc4_1: usdhc4grp-1 { 265 pinctrl_usdhc4_1: usdhc4grp-1 {
265 fsl,pins = < 266 fsl,pins = <
266 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ 267 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
267 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ 268 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
268 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ 269 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
269 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ 270 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
270 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ 271 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
271 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ 272 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
272 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ 273 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
273 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ 274 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
274 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ 275 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
275 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ 276 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
276 >; 277 >;
277 }; 278 };
278 279
279 pinctrl_usdhc4_2: usdhc4grp-2 { 280 pinctrl_usdhc4_2: usdhc4grp-2 {
280 fsl,pins = < 281 fsl,pins = <
281 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ 282 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
282 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ 283 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
283 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ 284 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
284 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ 285 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
285 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ 286 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
286 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ 287 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
287 >; 288 >;
288 }; 289 };
289 }; 290 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 18:33:00 -0500