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authorShawn Guo <shawn.guo@linaro.org>2013-02-19 21:32:52 -0500
committerShawn Guo <shawn.guo@linaro.org>2013-04-09 10:52:50 -0400
commite16415313c9b00b1adc313e85c2c8a81febe0b98 (patch)
treeb1e804b1bb647f3984036d9f9befbe53023bc519 /arch/arm/boot/dts/imx53.dtsi
parent36dffd8f49bc1364998db81bee739ea4574d88f7 (diff)
pinctrl: imx: move hard-coding data into device tree
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx53.dtsi')
-rw-r--r--arch/arm/boot/dts/imx53.dtsi205
1 files changed, 103 insertions, 102 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index baea3b581046..98149ac5c841 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include "skeleton.dtsi" 13#include "skeleton.dtsi"
14#include "imx53-pinfunc.h"
14 15
15/ { 16/ {
16 aliases { 17 aliases {
@@ -249,10 +250,10 @@
249 audmux { 250 audmux {
250 pinctrl_audmux_1: audmuxgrp-1 { 251 pinctrl_audmux_1: audmuxgrp-1 {
251 fsl,pins = < 252 fsl,pins = <
252 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ 253 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
253 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ 254 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
254 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ 255 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
255 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ 256 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
256 >; 257 >;
257 }; 258 };
258 }; 259 };
@@ -260,16 +261,16 @@
260 fec { 261 fec {
261 pinctrl_fec_1: fecgrp-1 { 262 pinctrl_fec_1: fecgrp-1 {
262 fsl,pins = < 263 fsl,pins = <
263 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */ 264 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
264 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ 265 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
265 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ 266 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
266 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ 267 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
267 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ 268 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
268 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ 269 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
269 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ 270 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
270 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ 271 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
271 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ 272 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
272 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ 273 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
273 >; 274 >;
274 }; 275 };
275 }; 276 };
@@ -277,27 +278,27 @@
277 csi { 278 csi {
278 pinctrl_csi_1: csigrp-1 { 279 pinctrl_csi_1: csigrp-1 {
279 fsl,pins = < 280 fsl,pins = <
280 286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */ 281 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
281 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */ 282 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
282 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */ 283 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
283 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ 284 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
284 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */ 285 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
285 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */ 286 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
286 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */ 287 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
287 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */ 288 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
288 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */ 289 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
289 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */ 290 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
290 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */ 291 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
291 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */ 292 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
292 352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */ 293 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
293 344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */ 294 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
294 336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */ 295 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
295 328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */ 296 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
296 320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */ 297 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
297 312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */ 298 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
298 304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */ 299 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
299 296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */ 300 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
300 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ 301 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
301 >; 302 >;
302 }; 303 };
303 }; 304 };
@@ -305,9 +306,9 @@
305 cspi { 306 cspi {
306 pinctrl_cspi_1: cspigrp-1 { 307 pinctrl_cspi_1: cspigrp-1 {
307 fsl,pins = < 308 fsl,pins = <
308 998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */ 309 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
309 1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */ 310 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
310 1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */ 311 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
311 >; 312 >;
312 }; 313 };
313 }; 314 };
@@ -315,9 +316,9 @@
315 ecspi1 { 316 ecspi1 {
316 pinctrl_ecspi1_1: ecspi1grp-1 { 317 pinctrl_ecspi1_1: ecspi1grp-1 {
317 fsl,pins = < 318 fsl,pins = <
318 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ 319 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
319 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ 320 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
320 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ 321 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
321 >; 322 >;
322 }; 323 };
323 }; 324 };
@@ -325,27 +326,27 @@
325 esdhc1 { 326 esdhc1 {
326 pinctrl_esdhc1_1: esdhc1grp-1 { 327 pinctrl_esdhc1_1: esdhc1grp-1 {
327 fsl,pins = < 328 fsl,pins = <
328 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ 329 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
329 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ 330 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
330 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ 331 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
331 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ 332 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
332 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ 333 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
333 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ 334 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
334 >; 335 >;
335 }; 336 };
336 337
337 pinctrl_esdhc1_2: esdhc1grp-2 { 338 pinctrl_esdhc1_2: esdhc1grp-2 {
338 fsl,pins = < 339 fsl,pins = <
339 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ 340 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
340 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ 341 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
341 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ 342 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
342 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ 343 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
343 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ 344 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
344 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ 345 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
345 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ 346 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
346 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ 347 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
347 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ 348 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
348 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ 349 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
349 >; 350 >;
350 }; 351 };
351 }; 352 };
@@ -353,12 +354,12 @@
353 esdhc2 { 354 esdhc2 {
354 pinctrl_esdhc2_1: esdhc2grp-1 { 355 pinctrl_esdhc2_1: esdhc2grp-1 {
355 fsl,pins = < 356 fsl,pins = <
356 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ 357 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
357 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ 358 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
358 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ 359 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
359 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ 360 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
360 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ 361 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
361 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ 362 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
362 >; 363 >;
363 }; 364 };
364 }; 365 };
@@ -366,16 +367,16 @@
366 esdhc3 { 367 esdhc3 {
367 pinctrl_esdhc3_1: esdhc3grp-1 { 368 pinctrl_esdhc3_1: esdhc3grp-1 {
368 fsl,pins = < 369 fsl,pins = <
369 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ 370 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
370 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ 371 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
371 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ 372 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
372 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ 373 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
373 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ 374 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
374 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ 375 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
375 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ 376 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
376 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ 377 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
377 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ 378 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
378 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ 379 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
379 >; 380 >;
380 }; 381 };
381 }; 382 };
@@ -383,15 +384,15 @@
383 can1 { 384 can1 {
384 pinctrl_can1_1: can1grp-1 { 385 pinctrl_can1_1: can1grp-1 {
385 fsl,pins = < 386 fsl,pins = <
386 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */ 387 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
387 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ 388 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
388 >; 389 >;
389 }; 390 };
390 391
391 pinctrl_can1_2: can1grp-2 { 392 pinctrl_can1_2: can1grp-2 {
392 fsl,pins = < 393 fsl,pins = <
393 37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */ 394 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
394 44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */ 395 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
395 >; 396 >;
396 }; 397 };
397 }; 398 };
@@ -399,8 +400,8 @@
399 can2 { 400 can2 {
400 pinctrl_can2_1: can2grp-1 { 401 pinctrl_can2_1: can2grp-1 {
401 fsl,pins = < 402 fsl,pins = <
402 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */ 403 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
403 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */ 404 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
404 >; 405 >;
405 }; 406 };
406 }; 407 };
@@ -408,8 +409,8 @@
408 i2c1 { 409 i2c1 {
409 pinctrl_i2c1_1: i2c1grp-1 { 410 pinctrl_i2c1_1: i2c1grp-1 {
410 fsl,pins = < 411 fsl,pins = <
411 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ 412 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
412 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ 413 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
413 >; 414 >;
414 }; 415 };
415 }; 416 };
@@ -417,8 +418,8 @@
417 i2c2 { 418 i2c2 {
418 pinctrl_i2c2_1: i2c2grp-1 { 419 pinctrl_i2c2_1: i2c2grp-1 {
419 fsl,pins = < 420 fsl,pins = <
420 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ 421 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
421 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */ 422 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
422 >; 423 >;
423 }; 424 };
424 }; 425 };
@@ -426,8 +427,8 @@
426 i2c3 { 427 i2c3 {
427 pinctrl_i2c3_1: i2c3grp-1 { 428 pinctrl_i2c3_1: i2c3grp-1 {
428 fsl,pins = < 429 fsl,pins = <
429 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */ 430 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
430 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */ 431 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
431 >; 432 >;
432 }; 433 };
433 }; 434 };
@@ -435,7 +436,7 @@
435 owire { 436 owire {
436 pinctrl_owire_1: owiregrp-1 { 437 pinctrl_owire_1: owiregrp-1 {
437 fsl,pins = < 438 fsl,pins = <
438 1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */ 439 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
439 >; 440 >;
440 }; 441 };
441 }; 442 };
@@ -443,15 +444,15 @@
443 uart1 { 444 uart1 {
444 pinctrl_uart1_1: uart1grp-1 { 445 pinctrl_uart1_1: uart1grp-1 {
445 fsl,pins = < 446 fsl,pins = <
446 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ 447 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
447 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ 448 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
448 >; 449 >;
449 }; 450 };
450 451
451 pinctrl_uart1_2: uart1grp-2 { 452 pinctrl_uart1_2: uart1grp-2 {
452 fsl,pins = < 453 fsl,pins = <
453 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ 454 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
454 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ 455 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
455 >; 456 >;
456 }; 457 };
457 }; 458 };
@@ -459,8 +460,8 @@
459 uart2 { 460 uart2 {
460 pinctrl_uart2_1: uart2grp-1 { 461 pinctrl_uart2_1: uart2grp-1 {
461 fsl,pins = < 462 fsl,pins = <
462 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ 463 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
463 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ 464 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
464 >; 465 >;
465 }; 466 };
466 }; 467 };
@@ -468,17 +469,17 @@
468 uart3 { 469 uart3 {
469 pinctrl_uart3_1: uart3grp-1 { 470 pinctrl_uart3_1: uart3grp-1 {
470 fsl,pins = < 471 fsl,pins = <
471 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ 472 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
472 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ 473 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
473 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ 474 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
474 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ 475 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
475 >; 476 >;
476 }; 477 };
477 478
478 pinctrl_uart3_2: uart3grp-2 { 479 pinctrl_uart3_2: uart3grp-2 {
479 fsl,pins = < 480 fsl,pins = <
480 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ 481 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
481 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ 482 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
482 >; 483 >;
483 }; 484 };
484 485
@@ -487,8 +488,8 @@
487 uart4 { 488 uart4 {
488 pinctrl_uart4_1: uart4grp-1 { 489 pinctrl_uart4_1: uart4grp-1 {
489 fsl,pins = < 490 fsl,pins = <
490 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */ 491 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
491 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */ 492 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
492 >; 493 >;
493 }; 494 };
494 }; 495 };
@@ -496,8 +497,8 @@
496 uart5 { 497 uart5 {
497 pinctrl_uart5_1: uart5grp-1 { 498 pinctrl_uart5_1: uart5grp-1 {
498 fsl,pins = < 499 fsl,pins = <
499 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */ 500 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
500 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */ 501 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
501 >; 502 >;
502 }; 503 };
503 }; 504 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 20:11:06 -0500