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authorRoland Stigge <stigge@antcom.de>2012-10-25 07:26:39 -0400
committerShawn Guo <shawn.guo@linaro.org>2012-11-16 01:18:53 -0500
commita1fff236b43dfe6394fd04b0302f5a261e1cc3e5 (patch)
tree03a3d0f5320ac76ec58cf030e1a94563a7ee08cd /arch/arm/boot/dts/imx53.dtsi
parentd90df97863c7838847abd0f144c71db60aa00643 (diff)
ARM: dts: imx53: pinctl update
This patch supplements pinctl support on i.MX53. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx53.dtsi')
-rw-r--r--arch/arm/boot/dts/imx53.dtsi46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index a5dd4ce6fd02..8b33195a5a33 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -320,6 +320,24 @@
320 }; 320 };
321 }; 321 };
322 322
323 can1 {
324 pinctrl_can1_1: can1grp-1 {
325 fsl,pins = <
326 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
327 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
328 >;
329 };
330 };
331
332 can2 {
333 pinctrl_can2_1: can2grp-1 {
334 fsl,pins = <
335 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
336 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
337 >;
338 };
339 };
340
323 i2c1 { 341 i2c1 {
324 pinctrl_i2c1_1: i2c1grp-1 { 342 pinctrl_i2c1_1: i2c1grp-1 {
325 fsl,pins = < 343 fsl,pins = <
@@ -338,6 +356,15 @@
338 }; 356 };
339 }; 357 };
340 358
359 i2c3 {
360 pinctrl_i2c3_1: i2c3grp-1 {
361 fsl,pins = <
362 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
363 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
364 >;
365 };
366 };
367
341 uart1 { 368 uart1 {
342 pinctrl_uart1_1: uart1grp-1 { 369 pinctrl_uart1_1: uart1grp-1 {
343 fsl,pins = < 370 fsl,pins = <
@@ -373,6 +400,25 @@
373 >; 400 >;
374 }; 401 };
375 }; 402 };
403
404 uart4 {
405 pinctrl_uart4_1: uart4grp-1 {
406 fsl,pins = <
407 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
408 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
409 >;
410 };
411 };
412
413 uart5 {
414 pinctrl_uart5_1: uart5grp-1 {
415 fsl,pins = <
416 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
417 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
418 >;
419 };
420 };
421
376 }; 422 };
377 423
378 uart1: serial@53fbc000 { 424 uart1: serial@53fbc000 {