pinctrl: imx: move hard-coding data into device tree

Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function.  Every time a new imx SoC support is
added, we need to add such a big mount of data.  With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.

With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.

The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.

As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 7 insertions, 7 deletions

diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 054db3b8f83f..6dd9486c755b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -222,13 +222,13 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                694  0x20d5     /* MX51_PAD_GPIO1_0__SD1_CD */
-                                697  0x20d5     /* MX51_PAD_GPIO1_1__SD1_WP */
-                                737  0x100      /* MX51_PAD_GPIO1_5__GPIO1_5 */
-                                740  0x100      /* MX51_PAD_GPIO1_6__GPIO1_6 */
-                                121  0x5        /* MX51_PAD_EIM_A27__GPIO2_21 */
-                                402  0x85       /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
-                                405  0x85       /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+                                MX51_PAD_GPIO1_0__SD1_CD     0x20d5
+                                MX51_PAD_GPIO1_1__SD1_WP     0x20d5
+                                MX51_PAD_GPIO1_5__GPIO1_5    0x100
+                                MX51_PAD_GPIO1_6__GPIO1_6    0x100
+                                MX51_PAD_EIM_A27__GPIO2_21   0x5
+                                MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
+                                MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
                         >;
                 };
         };