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authorSascha Hauer <s.hauer@pengutronix.de>2014-05-08 02:17:30 -0400
committerShawn Guo <shawn.guo@freescale.com>2014-05-16 11:02:09 -0400
commitc73dbd71117bc2a6eb0253add0dbcedf4b097e8b (patch)
tree70f4b5369a11921a9fcef7b967a2e07e73607e3b /arch/arm/boot/dts/imx51-babbage.dts
parente02ab39a2edf95aed487f7d25daa39a93eaf746c (diff)
ARM: dts: i.MX51 babbage: Fix FEC pad ctrl settings
The dts relied on the FEC pad ctrl settings from the bootloader by using the NO_PAD_CTRL option. This breaks once the bootloader starts initializing the pad ctrl settings from the same dts file. Change to real pad ctrl settings taken from the platform based babbage support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx51-babbage.dts')
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts37
1 files changed, 19 insertions, 18 deletions
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 15062a3164a3..6bc3243a80d3 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -488,24 +488,25 @@
488 488
489 pinctrl_fec: fecgrp { 489 pinctrl_fec: fecgrp {
490 fsl,pins = < 490 fsl,pins = <
491 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000 491 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
492 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000 492 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
493 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000 493 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
494 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000 494 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
495 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000 495 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
496 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000 496 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
497 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000 497 MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
498 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000 498 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
499 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000 499 MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
500 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000 500 MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
501 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000 501 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
502 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000 502 MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
503 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000 503 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
504 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000 504 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
505 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000 505 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
506 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000 506 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
507 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000 507 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
508 MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */ 508 MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
509 MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
509 >; 510 >;
510 }; 511 };
511 512