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authorAlexander Shiyan <shc_work@mail.ru>2013-11-30 01:18:04 -0500
committerShawn Guo <shawn.guo@linaro.org>2014-02-09 08:33:09 -0500
commit6ece55b39218d35d44e050d6e47b28a6489edd2b (patch)
tree5e6aa758a60d94de6db506bfbe34cc32e4321e66 /arch/arm/boot/dts/imx27-phytec-phycore-som.dts
parentf64ba746827ea23510659ebcacc84a1c6120eda4 (diff)
ARM: dts: i.MX27 boards: Switch to use standard GPIO and IRQ flags definitions
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx27-phytec-phycore-som.dts')
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index 07fd4be8cd36..dd26e1588a58 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -52,7 +52,7 @@
52 52
53&cspi1 { 53&cspi1 {
54 fsl,spi-num-chipselects = <1>; 54 fsl,spi-num-chipselects = <1>;
55 cs-gpios = <&gpio4 28 0>; 55 cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
56 status = "okay"; 56 status = "okay";
57 57
58 pmic: mc13783@0 { 58 pmic: mc13783@0 {
@@ -62,7 +62,7 @@
62 spi-max-frequency = <20000000>; 62 spi-max-frequency = <20000000>;
63 reg = <0>; 63 reg = <0>;
64 interrupt-parent = <&gpio2>; 64 interrupt-parent = <&gpio2>;
65 interrupts = <23 0x4>; 65 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
66 fsl,mc13xxx-uses-adc; 66 fsl,mc13xxx-uses-adc;
67 fsl,mc13xxx-uses-rtc; 67 fsl,mc13xxx-uses-rtc;
68 68
@@ -149,7 +149,7 @@
149 149
150&fec { 150&fec {
151 phy-mode = "mii"; 151 phy-mode = "mii";
152 phy-reset-gpios = <&gpio3 30 0>; 152 phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
153 phy-supply = <&reg_3v3>; 153 phy-supply = <&reg_3v3>;
154 pinctrl-names = "default"; 154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_fec1>; 155 pinctrl-0 = <&pinctrl_fec1>;