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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-12 15:05:15 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-12 15:05:15 -0500
commitd027db132b395dabfac208e52a7e510e441bb9d2 (patch)
tree24b055b2385f9848e77e646ce475991d8675c3c4 /arch/arm/boot/dts/highbank.dts
parentd01e4afdbb65e030fd6f1f96c30a558e2eb0f279 (diff)
parent5faf7cbb848da827f6ea1458b5a1c26a44e7510a (diff)
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates from Olof Johansson: "This contains the bulk of new SoC development for this merge window. Two new platforms have been added, the sunxi platforms (Allwinner A1x SoCs) by Maxime Ripard, and a generic Broadcom platform for a new series of ARMv7 platforms from them, where the hope is that we can keep the platform code generic enough to have them all share one mach directory. The new Broadcom platform is contributed by Christian Daudt. Highbank has grown support for Calxeda's next generation of hardware, ECX-2000. clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also taken on maintainership of the platform. Beyond this there has been a bunch of work from a number of people on converting more platforms to IRQ domains, pinctrl conversion, cleanup and general feature enablement across most of the active platforms." Fix up trivial conflicts as per Olof. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits) mfd: vexpress-sysreg: Remove LEDs code irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids irq: versatile: delete dangling variable ARM: sunxi: add missing include for mdelay() ARM: EXYNOS: Avoid early use of of_machine_is_compatible() ARM: dts: add node for PL330 MDMA1 controller for exynos4 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412 ARM: EXYNOS: add UART3 to DEBUG_LL ports ARM: S3C24XX: Add clkdev entry for camif-upll clock ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers ARM: sunxi: Add missing sun4i.dtsi file pinctrl: samsung: Do not initialise statics to 0 ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup ...
Diffstat (limited to 'arch/arm/boot/dts/highbank.dts')
-rw-r--r--arch/arm/boot/dts/highbank.dts212
1 files changed, 3 insertions, 209 deletions
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 0c6fc34821f9..a9ae5d32e80d 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -69,16 +69,8 @@
69 reg = <0x00000000 0xff900000>; 69 reg = <0x00000000 0xff900000>;
70 }; 70 };
71 71
72 chosen {
73 bootargs = "console=ttyAMA0";
74 };
75
76 soc { 72 soc {
77 #address-cells = <1>; 73 ranges = <0x00000000 0x00000000 0xffffffff>;
78 #size-cells = <1>;
79 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
81 ranges;
82 74
83 timer@fff10600 { 75 timer@fff10600 {
84 compatible = "arm,cortex-a9-twd-timer"; 76 compatible = "arm,cortex-a9-twd-timer";
@@ -117,173 +109,6 @@
117 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; 109 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
118 }; 110 };
119 111
120 sata@ffe08000 {
121 compatible = "calxeda,hb-ahci";
122 reg = <0xffe08000 0x10000>;
123 interrupts = <0 83 4>;
124 calxeda,port-phys = <&combophy5 0 &combophy0 0
125 &combophy0 1 &combophy0 2
126 &combophy0 3>;
127 dma-coherent;
128 };
129
130 sdhci@ffe0e000 {
131 compatible = "calxeda,hb-sdhci";
132 reg = <0xffe0e000 0x1000>;
133 interrupts = <0 90 4>;
134 clocks = <&eclk>;
135 };
136
137 memory-controller@fff00000 {
138 compatible = "calxeda,hb-ddr-ctrl";
139 reg = <0xfff00000 0x1000>;
140 interrupts = <0 91 4>;
141 };
142
143 ipc@fff20000 {
144 compatible = "arm,pl320", "arm,primecell";
145 reg = <0xfff20000 0x1000>;
146 interrupts = <0 7 4>;
147 clocks = <&pclk>;
148 clock-names = "apb_pclk";
149 };
150
151 gpioe: gpio@fff30000 {
152 #gpio-cells = <2>;
153 compatible = "arm,pl061", "arm,primecell";
154 gpio-controller;
155 reg = <0xfff30000 0x1000>;
156 interrupts = <0 14 4>;
157 clocks = <&pclk>;
158 clock-names = "apb_pclk";
159 };
160
161 gpiof: gpio@fff31000 {
162 #gpio-cells = <2>;
163 compatible = "arm,pl061", "arm,primecell";
164 gpio-controller;
165 reg = <0xfff31000 0x1000>;
166 interrupts = <0 15 4>;
167 clocks = <&pclk>;
168 clock-names = "apb_pclk";
169 };
170
171 gpiog: gpio@fff32000 {
172 #gpio-cells = <2>;
173 compatible = "arm,pl061", "arm,primecell";
174 gpio-controller;
175 reg = <0xfff32000 0x1000>;
176 interrupts = <0 16 4>;
177 clocks = <&pclk>;
178 clock-names = "apb_pclk";
179 };
180
181 gpioh: gpio@fff33000 {
182 #gpio-cells = <2>;
183 compatible = "arm,pl061", "arm,primecell";
184 gpio-controller;
185 reg = <0xfff33000 0x1000>;
186 interrupts = <0 17 4>;
187 clocks = <&pclk>;
188 clock-names = "apb_pclk";
189 };
190
191 timer {
192 compatible = "arm,sp804", "arm,primecell";
193 reg = <0xfff34000 0x1000>;
194 interrupts = <0 18 4>;
195 clocks = <&pclk>;
196 clock-names = "apb_pclk";
197 };
198
199 rtc@fff35000 {
200 compatible = "arm,pl031", "arm,primecell";
201 reg = <0xfff35000 0x1000>;
202 interrupts = <0 19 4>;
203 clocks = <&pclk>;
204 clock-names = "apb_pclk";
205 };
206
207 serial@fff36000 {
208 compatible = "arm,pl011", "arm,primecell";
209 reg = <0xfff36000 0x1000>;
210 interrupts = <0 20 4>;
211 clocks = <&pclk>;
212 clock-names = "apb_pclk";
213 };
214
215 smic@fff3a000 {
216 compatible = "ipmi-smic";
217 device_type = "ipmi";
218 reg = <0xfff3a000 0x1000>;
219 interrupts = <0 24 4>;
220 reg-size = <4>;
221 reg-spacing = <4>;
222 };
223
224 sregs@fff3c000 {
225 compatible = "calxeda,hb-sregs";
226 reg = <0xfff3c000 0x1000>;
227
228 clocks {
229 #address-cells = <1>;
230 #size-cells = <0>;
231
232 osc: oscillator {
233 #clock-cells = <0>;
234 compatible = "fixed-clock";
235 clock-frequency = <33333000>;
236 };
237
238 ddrpll: ddrpll {
239 #clock-cells = <0>;
240 compatible = "calxeda,hb-pll-clock";
241 clocks = <&osc>;
242 reg = <0x108>;
243 };
244
245 a9pll: a9pll {
246 #clock-cells = <0>;
247 compatible = "calxeda,hb-pll-clock";
248 clocks = <&osc>;
249 reg = <0x100>;
250 };
251
252 a9periphclk: a9periphclk {
253 #clock-cells = <0>;
254 compatible = "calxeda,hb-a9periph-clock";
255 clocks = <&a9pll>;
256 reg = <0x104>;
257 };
258
259 a9bclk: a9bclk {
260 #clock-cells = <0>;
261 compatible = "calxeda,hb-a9bus-clock";
262 clocks = <&a9pll>;
263 reg = <0x104>;
264 };
265
266 emmcpll: emmcpll {
267 #clock-cells = <0>;
268 compatible = "calxeda,hb-pll-clock";
269 clocks = <&osc>;
270 reg = <0x10C>;
271 };
272
273 eclk: eclk {
274 #clock-cells = <0>;
275 compatible = "calxeda,hb-emmc-clock";
276 clocks = <&emmcpll>;
277 reg = <0x114>;
278 };
279
280 pclk: pclk {
281 #clock-cells = <0>;
282 compatible = "fixed-clock";
283 clock-frequency = <150000000>;
284 };
285 };
286 };
287 112
288 sregs@fff3c200 { 113 sregs@fff3c200 {
289 compatible = "calxeda,hb-sregs-l2-ecc"; 114 compatible = "calxeda,hb-sregs-l2-ecc";
@@ -291,38 +116,7 @@
291 interrupts = <0 71 4 0 72 4>; 116 interrupts = <0 71 4 0 72 4>;
292 }; 117 };
293 118
294 dma@fff3d000 {
295 compatible = "arm,pl330", "arm,primecell";
296 reg = <0xfff3d000 0x1000>;
297 interrupts = <0 92 4>;
298 clocks = <&pclk>;
299 clock-names = "apb_pclk";
300 };
301
302 ethernet@fff50000 {
303 compatible = "calxeda,hb-xgmac";
304 reg = <0xfff50000 0x1000>;
305 interrupts = <0 77 4 0 78 4 0 79 4>;
306 };
307
308 ethernet@fff51000 {
309 compatible = "calxeda,hb-xgmac";
310 reg = <0xfff51000 0x1000>;
311 interrupts = <0 80 4 0 81 4 0 82 4>;
312 };
313
314 combophy0: combo-phy@fff58000 {
315 compatible = "calxeda,hb-combophy";
316 #phy-cells = <1>;
317 reg = <0xfff58000 0x1000>;
318 phydev = <5>;
319 };
320
321 combophy5: combo-phy@fff5d000 {
322 compatible = "calxeda,hb-combophy";
323 #phy-cells = <1>;
324 reg = <0xfff5d000 0x1000>;
325 phydev = <31>;
326 };
327 }; 119 };
328}; 120};
121
122/include/ "ecx-common.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 06:09:38 -0500