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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2013-07-29 08:31:53 -0400
committerJason Cooper <jason@lakedaemon.net>2013-09-30 11:00:47 -0400
commit0ad44659355d5c2efdd5b6c1de165ca31cb34fa8 (patch)
tree57f2d1d749248e046d288e574bc3ea0eb39114e2 /arch/arm/boot/dts/dove.dtsi
parent960ee4e7967f0d0bdebae439e79f94cec78e23f7 (diff)
ARM: dove: relocate internal registers device nodes
With mbus node in place, now relocate all internal device nodes to internal-regs node with proper address ranges. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/dove.dtsi')
-rw-r--r--arch/arm/boot/dts/dove.dtsi955
1 files changed, 474 insertions, 481 deletions
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index d312290edfc1..d42b323e7593 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -5,6 +5,7 @@
5/ { 5/ {
6 compatible = "marvell,dove"; 6 compatible = "marvell,dove";
7 model = "Marvell Armada 88AP510 SoC"; 7 model = "Marvell Armada 88AP510 SoC";
8 interrupt-parent = <&intc>;
8 9
9 aliases { 10 aliases {
10 gpio0 = &gpio0; 11 gpio0 = &gpio0;
@@ -42,489 +43,481 @@
42 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ 43 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
43 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ 44 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
44 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ 45 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
45 };
46
47 soc@f1000000 {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&intc>;
52
53 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
54 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
55 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
56 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
57 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
58 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
59 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
60 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
61
62 mbusc: mbus-ctrl@20000 {
63 compatible = "marvell,mbus-controller";
64 reg = <0x20000 0x80>, <0x800100 0x8>;
65 };
66
67 timer: timer@20300 {
68 compatible = "marvell,orion-timer";
69 reg = <0x20300 0x20>;
70 interrupt-parent = <&bridge_intc>;
71 interrupts = <1>, <2>;
72 clocks = <&core_clk 0>;
73 };
74
75 intc: main-interrupt-ctrl@20200 {
76 compatible = "marvell,orion-intc";
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x20200 0x10>, <0x20210 0x10>;
80 };
81
82 bridge_intc: bridge-interrupt-ctrl@20110 {
83 compatible = "marvell,orion-bridge-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 reg = <0x20110 0x8>;
87 interrupts = <0>;
88 marvell,#interrupts = <5>;
89 };
90
91 core_clk: core-clocks@d0214 {
92 compatible = "marvell,dove-core-clock";
93 reg = <0xd0214 0x4>;
94 #clock-cells = <1>;
95 };
96
97 gate_clk: clock-gating-ctrl@d0038 {
98 compatible = "marvell,dove-gating-clock";
99 reg = <0xd0038 0x4>;
100 clocks = <&core_clk 0>;
101 #clock-cells = <1>;
102 };
103
104 thermal: thermal-diode@d001c {
105 compatible = "marvell,dove-thermal";
106 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
107 };
108
109 uart0: serial@12000 {
110 compatible = "ns16550a";
111 reg = <0x12000 0x100>;
112 reg-shift = <2>;
113 interrupts = <7>;
114 clocks = <&core_clk 0>;
115 status = "disabled";
116 };
117
118 uart1: serial@12100 {
119 compatible = "ns16550a";
120 reg = <0x12100 0x100>;
121 reg-shift = <2>;
122 interrupts = <8>;
123 clocks = <&core_clk 0>;
124 pinctrl-0 = <&pmx_uart1>;
125 pinctrl-names = "default";
126 status = "disabled";
127 };
128
129 uart2: serial@12200 {
130 compatible = "ns16550a";
131 reg = <0x12000 0x100>;
132 reg-shift = <2>;
133 interrupts = <9>;
134 clocks = <&core_clk 0>;
135 status = "disabled";
136 };
137
138 uart3: serial@12300 {
139 compatible = "ns16550a";
140 reg = <0x12100 0x100>;
141 reg-shift = <2>;
142 interrupts = <10>;
143 clocks = <&core_clk 0>;
144 status = "disabled";
145 };
146
147 gpio0: gpio-ctrl@d0400 {
148 compatible = "marvell,orion-gpio";
149 #gpio-cells = <2>;
150 gpio-controller;
151 reg = <0xd0400 0x20>;
152 ngpios = <32>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
155 interrupts = <12>, <13>, <14>, <60>;
156 };
157
158 gpio1: gpio-ctrl@d0420 {
159 compatible = "marvell,orion-gpio";
160 #gpio-cells = <2>;
161 gpio-controller;
162 reg = <0xd0420 0x20>;
163 ngpios = <32>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 interrupts = <61>;
167 };
168
169 gpio2: gpio-ctrl@e8400 {
170 compatible = "marvell,orion-gpio";
171 #gpio-cells = <2>;
172 gpio-controller;
173 reg = <0xe8400 0x0c>;
174 ngpios = <8>;
175 };
176
177 pinctrl: pin-ctrl@d0200 {
178 compatible = "marvell,dove-pinctrl";
179 reg = <0xd0200 0x10>;
180 clocks = <&gate_clk 22>;
181
182 pmx_gpio_0: pmx-gpio-0 {
183 marvell,pins = "mpp0";
184 marvell,function = "gpio";
185 };
186
187 pmx_gpio_1: pmx-gpio-1 {
188 marvell,pins = "mpp1";
189 marvell,function = "gpio";
190 };
191
192 pmx_gpio_2: pmx-gpio-2 {
193 marvell,pins = "mpp2";
194 marvell,function = "gpio";
195 };
196
197 pmx_gpio_3: pmx-gpio-3 {
198 marvell,pins = "mpp3";
199 marvell,function = "gpio";
200 };
201
202 pmx_gpio_4: pmx-gpio-4 {
203 marvell,pins = "mpp4";
204 marvell,function = "gpio";
205 };
206
207 pmx_gpio_5: pmx-gpio-5 {
208 marvell,pins = "mpp5";
209 marvell,function = "gpio";
210 };
211
212 pmx_gpio_6: pmx-gpio-6 {
213 marvell,pins = "mpp6";
214 marvell,function = "gpio";
215 };
216
217 pmx_gpio_7: pmx-gpio-7 {
218 marvell,pins = "mpp7";
219 marvell,function = "gpio";
220 };
221
222 pmx_gpio_8: pmx-gpio-8 {
223 marvell,pins = "mpp8";
224 marvell,function = "gpio";
225 };
226
227 pmx_gpio_9: pmx-gpio-9 {
228 marvell,pins = "mpp9";
229 marvell,function = "gpio";
230 };
231
232 pmx_gpio_10: pmx-gpio-10 {
233 marvell,pins = "mpp10";
234 marvell,function = "gpio";
235 };
236
237 pmx_gpio_11: pmx-gpio-11 {
238 marvell,pins = "mpp11";
239 marvell,function = "gpio";
240 };
241
242 pmx_gpio_12: pmx-gpio-12 {
243 marvell,pins = "mpp12";
244 marvell,function = "gpio";
245 };
246
247 pmx_gpio_13: pmx-gpio-13 {
248 marvell,pins = "mpp13";
249 marvell,function = "gpio";
250 };
251
252 pmx_gpio_14: pmx-gpio-14 {
253 marvell,pins = "mpp14";
254 marvell,function = "gpio";
255 };
256
257 pmx_gpio_15: pmx-gpio-15 {
258 marvell,pins = "mpp15";
259 marvell,function = "gpio";
260 };
261
262 pmx_gpio_16: pmx-gpio-16 {
263 marvell,pins = "mpp16";
264 marvell,function = "gpio";
265 };
266
267 pmx_gpio_17: pmx-gpio-17 {
268 marvell,pins = "mpp17";
269 marvell,function = "gpio";
270 };
271
272 pmx_gpio_18: pmx-gpio-18 {
273 marvell,pins = "mpp18";
274 marvell,function = "gpio";
275 };
276
277 pmx_gpio_19: pmx-gpio-19 {
278 marvell,pins = "mpp19";
279 marvell,function = "gpio";
280 };
281
282 pmx_gpio_20: pmx-gpio-20 {
283 marvell,pins = "mpp20";
284 marvell,function = "gpio";
285 };
286
287 pmx_gpio_21: pmx-gpio-21 {
288 marvell,pins = "mpp21";
289 marvell,function = "gpio";
290 };
291
292 pmx_camera: pmx-camera {
293 marvell,pins = "mpp_camera";
294 marvell,function = "camera";
295 };
296
297 pmx_camera_gpio: pmx-camera-gpio {
298 marvell,pins = "mpp_camera";
299 marvell,function = "gpio";
300 };
301
302 pmx_sdio0: pmx-sdio0 {
303 marvell,pins = "mpp_sdio0";
304 marvell,function = "sdio0";
305 };
306
307 pmx_sdio0_gpio: pmx-sdio0-gpio {
308 marvell,pins = "mpp_sdio0";
309 marvell,function = "gpio";
310 };
311
312 pmx_sdio1: pmx-sdio1 {
313 marvell,pins = "mpp_sdio1";
314 marvell,function = "sdio1";
315 };
316
317 pmx_sdio1_gpio: pmx-sdio1-gpio {
318 marvell,pins = "mpp_sdio1";
319 marvell,function = "gpio";
320 };
321
322 pmx_audio1_gpio: pmx-audio1-gpio {
323 marvell,pins = "mpp_audio1";
324 marvell,function = "gpio";
325 };
326
327 pmx_spi0: pmx-spi0 {
328 marvell,pins = "mpp_spi0";
329 marvell,function = "spi0";
330 };
331
332 pmx_spi0_gpio: pmx-spi0-gpio {
333 marvell,pins = "mpp_spi0";
334 marvell,function = "gpio";
335 };
336
337 pmx_uart1: pmx-uart1 {
338 marvell,pins = "mpp_uart1";
339 marvell,function = "uart1";
340 };
341
342 pmx_uart1_gpio: pmx-uart1-gpio {
343 marvell,pins = "mpp_uart1";
344 marvell,function = "gpio";
345 };
346
347 pmx_nand: pmx-nand {
348 marvell,pins = "mpp_nand";
349 marvell,function = "nand";
350 };
351
352 pmx_nand_gpo: pmx-nand-gpo {
353 marvell,pins = "mpp_nand";
354 marvell,function = "gpo";
355 };
356 };
357
358 spi0: spi-ctrl@10600 {
359 compatible = "marvell,orion-spi";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 cell-index = <0>;
363 interrupts = <6>;
364 reg = <0x10600 0x28>;
365 clocks = <&core_clk 0>;
366 pinctrl-0 = <&pmx_spi0>;
367 pinctrl-names = "default";
368 status = "disabled";
369 };
370
371 spi1: spi-ctrl@14600 {
372 compatible = "marvell,orion-spi";
373 #address-cells = <1>;
374 #size-cells = <0>;
375 cell-index = <1>;
376 interrupts = <5>;
377 reg = <0x14600 0x28>;
378 clocks = <&core_clk 0>;
379 status = "disabled";
380 };
381
382 i2c0: i2c-ctrl@11000 {
383 compatible = "marvell,mv64xxx-i2c";
384 reg = <0x11000 0x20>;
385 #address-cells = <1>;
386 #size-cells = <0>;
387 interrupts = <11>;
388 clock-frequency = <400000>;
389 timeout-ms = <1000>;
390 clocks = <&core_clk 0>;
391 status = "disabled";
392 };
393
394 ehci0: usb-host@50000 {
395 compatible = "marvell,orion-ehci";
396 reg = <0x50000 0x1000>;
397 interrupts = <24>;
398 clocks = <&gate_clk 0>;
399 status = "okay";
400 };
401
402 ehci1: usb-host@51000 {
403 compatible = "marvell,orion-ehci";
404 reg = <0x51000 0x1000>;
405 interrupts = <25>;
406 clocks = <&gate_clk 1>;
407 status = "okay";
408 };
409
410 sdio0: sdio-host@92000 {
411 compatible = "marvell,dove-sdhci";
412 reg = <0x92000 0x100>;
413 interrupts = <35>, <37>;
414 clocks = <&gate_clk 8>;
415 pinctrl-0 = <&pmx_sdio0>;
416 pinctrl-names = "default";
417 status = "disabled";
418 };
419
420 sdio1: sdio-host@90000 {
421 compatible = "marvell,dove-sdhci";
422 reg = <0x90000 0x100>;
423 interrupts = <36>, <38>;
424 clocks = <&gate_clk 9>;
425 pinctrl-0 = <&pmx_sdio1>;
426 pinctrl-names = "default";
427 status = "disabled";
428 };
429
430 sata0: sata-host@a0000 {
431 compatible = "marvell,orion-sata";
432 reg = <0xa0000 0x2400>;
433 interrupts = <62>;
434 clocks = <&gate_clk 3>;
435 nr-ports = <1>;
436 status = "disabled";
437 };
438
439 rtc: real-time-clock@d8500 {
440 compatible = "marvell,orion-rtc";
441 reg = <0xd8500 0x20>;
442 };
443
444 crypto: crypto-engine@30000 {
445 compatible = "marvell,orion-crypto";
446 reg = <0x30000 0x10000>,
447 <0xc8000000 0x800>;
448 reg-names = "regs", "sram";
449 interrupts = <31>;
450 clocks = <&gate_clk 15>;
451 status = "okay";
452 };
453
454 xor0: dma-engine@60800 {
455 compatible = "marvell,orion-xor";
456 reg = <0x60800 0x100
457 0x60a00 0x100>;
458 clocks = <&gate_clk 23>;
459 status = "okay";
460
461 channel0 {
462 interrupts = <39>;
463 dmacap,memcpy;
464 dmacap,xor;
465 };
466
467 channel1 {
468 interrupts = <40>;
469 dmacap,memset;
470 dmacap,memcpy;
471 dmacap,xor;
472 };
473 };
474
475 xor1: dma-engine@60900 {
476 compatible = "marvell,orion-xor";
477 reg = <0x60900 0x100
478 0x60b00 0x100>;
479 clocks = <&gate_clk 24>;
480 status = "okay";
481
482 channel0 {
483 interrupts = <42>;
484 dmacap,memcpy;
485 dmacap,xor;
486 };
487
488 channel1 {
489 interrupts = <43>;
490 dmacap,memset;
491 dmacap,memcpy;
492 dmacap,xor;
493 };
494 };
495
496 mdio: mdio-bus@72004 {
497 compatible = "marvell,orion-mdio";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 reg = <0x72004 0x84>;
501 interrupts = <30>;
502 clocks = <&gate_clk 2>;
503 status = "disabled";
504
505 ethphy: ethernet-phy {
506 device-type = "ethernet-phy";
507 /* set phy address in board file */
508 };
509 };
510 46
511 eth: ethernet-controller@72000 { 47 internal-regs {
512 compatible = "marvell,orion-eth"; 48 compatible = "simple-bus";
513 #address-cells = <1>; 49 #address-cells = <1>;
514 #size-cells = <0>; 50 #size-cells = <1>;
515 reg = <0x72000 0x4000>; 51 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
516 clocks = <&gate_clk 2>; 52 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
517 marvell,tx-checksum-limit = <1600>; 53 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
518 status = "disabled"; 54 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
519 55
520 ethernet-port@0 { 56 mbusc: mbus-ctrl@20000 {
521 device_type = "network"; 57 compatible = "marvell,mbus-controller";
522 compatible = "marvell,orion-eth-port"; 58 reg = <0x20000 0x80>, <0x800100 0x8>;
523 reg = <0>; 59 };
524 interrupts = <29>; 60
525 /* overwrite MAC address in bootloader */ 61 timer: timer@20300 {
526 local-mac-address = [00 00 00 00 00 00]; 62 compatible = "marvell,orion-timer";
527 phy-handle = <&ethphy>; 63 reg = <0x20300 0x20>;
64 interrupt-parent = <&bridge_intc>;
65 interrupts = <1>, <2>;
66 clocks = <&core_clk 0>;
67 };
68
69 intc: main-interrupt-ctrl@20200 {
70 compatible = "marvell,orion-intc";
71 interrupt-controller;
72 #interrupt-cells = <1>;
73 reg = <0x20200 0x10>, <0x20210 0x10>;
74 };
75
76 bridge_intc: bridge-interrupt-ctrl@20110 {
77 compatible = "marvell,orion-bridge-intc";
78 interrupt-controller;
79 #interrupt-cells = <1>;
80 reg = <0x20110 0x8>;
81 interrupts = <0>;
82 marvell,#interrupts = <5>;
83 };
84
85 core_clk: core-clocks@d0214 {
86 compatible = "marvell,dove-core-clock";
87 reg = <0xd0214 0x4>;
88 #clock-cells = <1>;
89 };
90
91 gate_clk: clock-gating-ctrl@d0038 {
92 compatible = "marvell,dove-gating-clock";
93 reg = <0xd0038 0x4>;
94 clocks = <&core_clk 0>;
95 #clock-cells = <1>;
96 };
97
98 thermal: thermal-diode@d001c {
99 compatible = "marvell,dove-thermal";
100 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
101 };
102
103 uart0: serial@12000 {
104 compatible = "ns16550a";
105 reg = <0x12000 0x100>;
106 reg-shift = <2>;
107 interrupts = <7>;
108 clocks = <&core_clk 0>;
109 status = "disabled";
110 };
111
112 uart1: serial@12100 {
113 compatible = "ns16550a";
114 reg = <0x12100 0x100>;
115 reg-shift = <2>;
116 interrupts = <8>;
117 clocks = <&core_clk 0>;
118 pinctrl-0 = <&pmx_uart1>;
119 pinctrl-names = "default";
120 status = "disabled";
121 };
122
123 uart2: serial@12200 {
124 compatible = "ns16550a";
125 reg = <0x12000 0x100>;
126 reg-shift = <2>;
127 interrupts = <9>;
128 clocks = <&core_clk 0>;
129 status = "disabled";
130 };
131
132 uart3: serial@12300 {
133 compatible = "ns16550a";
134 reg = <0x12100 0x100>;
135 reg-shift = <2>;
136 interrupts = <10>;
137 clocks = <&core_clk 0>;
138 status = "disabled";
139 };
140
141 gpio0: gpio-ctrl@d0400 {
142 compatible = "marvell,orion-gpio";
143 #gpio-cells = <2>;
144 gpio-controller;
145 reg = <0xd0400 0x20>;
146 ngpios = <32>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
149 interrupts = <12>, <13>, <14>, <60>;
150 };
151
152 gpio1: gpio-ctrl@d0420 {
153 compatible = "marvell,orion-gpio";
154 #gpio-cells = <2>;
155 gpio-controller;
156 reg = <0xd0420 0x20>;
157 ngpios = <32>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 interrupts = <61>;
161 };
162
163 gpio2: gpio-ctrl@e8400 {
164 compatible = "marvell,orion-gpio";
165 #gpio-cells = <2>;
166 gpio-controller;
167 reg = <0xe8400 0x0c>;
168 ngpios = <8>;
169 };
170
171 pinctrl: pin-ctrl@d0200 {
172 compatible = "marvell,dove-pinctrl";
173 reg = <0xd0200 0x10>;
174 clocks = <&gate_clk 22>;
175
176 pmx_gpio_0: pmx-gpio-0 {
177 marvell,pins = "mpp0";
178 marvell,function = "gpio";
179 };
180
181 pmx_gpio_1: pmx-gpio-1 {
182 marvell,pins = "mpp1";
183 marvell,function = "gpio";
184 };
185
186 pmx_gpio_2: pmx-gpio-2 {
187 marvell,pins = "mpp2";
188 marvell,function = "gpio";
189 };
190
191 pmx_gpio_3: pmx-gpio-3 {
192 marvell,pins = "mpp3";
193 marvell,function = "gpio";
194 };
195
196 pmx_gpio_4: pmx-gpio-4 {
197 marvell,pins = "mpp4";
198 marvell,function = "gpio";
199 };
200
201 pmx_gpio_5: pmx-gpio-5 {
202 marvell,pins = "mpp5";
203 marvell,function = "gpio";
204 };
205
206 pmx_gpio_6: pmx-gpio-6 {
207 marvell,pins = "mpp6";
208 marvell,function = "gpio";
209 };
210
211 pmx_gpio_7: pmx-gpio-7 {
212 marvell,pins = "mpp7";
213 marvell,function = "gpio";
214 };
215
216 pmx_gpio_8: pmx-gpio-8 {
217 marvell,pins = "mpp8";
218 marvell,function = "gpio";
219 };
220
221 pmx_gpio_9: pmx-gpio-9 {
222 marvell,pins = "mpp9";
223 marvell,function = "gpio";
224 };
225
226 pmx_gpio_10: pmx-gpio-10 {
227 marvell,pins = "mpp10";
228 marvell,function = "gpio";
229 };
230
231 pmx_gpio_11: pmx-gpio-11 {
232 marvell,pins = "mpp11";
233 marvell,function = "gpio";
234 };
235
236 pmx_gpio_12: pmx-gpio-12 {
237 marvell,pins = "mpp12";
238 marvell,function = "gpio";
239 };
240
241 pmx_gpio_13: pmx-gpio-13 {
242 marvell,pins = "mpp13";
243 marvell,function = "gpio";
244 };
245
246 pmx_gpio_14: pmx-gpio-14 {
247 marvell,pins = "mpp14";
248 marvell,function = "gpio";
249 };
250
251 pmx_gpio_15: pmx-gpio-15 {
252 marvell,pins = "mpp15";
253 marvell,function = "gpio";
254 };
255
256 pmx_gpio_16: pmx-gpio-16 {
257 marvell,pins = "mpp16";
258 marvell,function = "gpio";
259 };
260
261 pmx_gpio_17: pmx-gpio-17 {
262 marvell,pins = "mpp17";
263 marvell,function = "gpio";
264 };
265
266 pmx_gpio_18: pmx-gpio-18 {
267 marvell,pins = "mpp18";
268 marvell,function = "gpio";
269 };
270
271 pmx_gpio_19: pmx-gpio-19 {
272 marvell,pins = "mpp19";
273 marvell,function = "gpio";
274 };
275
276 pmx_gpio_20: pmx-gpio-20 {
277 marvell,pins = "mpp20";
278 marvell,function = "gpio";
279 };
280
281 pmx_gpio_21: pmx-gpio-21 {
282 marvell,pins = "mpp21";
283 marvell,function = "gpio";
284 };
285
286 pmx_camera: pmx-camera {
287 marvell,pins = "mpp_camera";
288 marvell,function = "camera";
289 };
290
291 pmx_camera_gpio: pmx-camera-gpio {
292 marvell,pins = "mpp_camera";
293 marvell,function = "gpio";
294 };
295
296 pmx_sdio0: pmx-sdio0 {
297 marvell,pins = "mpp_sdio0";
298 marvell,function = "sdio0";
299 };
300
301 pmx_sdio0_gpio: pmx-sdio0-gpio {
302 marvell,pins = "mpp_sdio0";
303 marvell,function = "gpio";
304 };
305
306 pmx_sdio1: pmx-sdio1 {
307 marvell,pins = "mpp_sdio1";
308 marvell,function = "sdio1";
309 };
310
311 pmx_sdio1_gpio: pmx-sdio1-gpio {
312 marvell,pins = "mpp_sdio1";
313 marvell,function = "gpio";
314 };
315
316 pmx_audio1_gpio: pmx-audio1-gpio {
317 marvell,pins = "mpp_audio1";
318 marvell,function = "gpio";
319 };
320
321 pmx_spi0: pmx-spi0 {
322 marvell,pins = "mpp_spi0";
323 marvell,function = "spi0";
324 };
325
326 pmx_spi0_gpio: pmx-spi0-gpio {
327 marvell,pins = "mpp_spi0";
328 marvell,function = "gpio";
329 };
330
331 pmx_uart1: pmx-uart1 {
332 marvell,pins = "mpp_uart1";
333 marvell,function = "uart1";
334 };
335
336 pmx_uart1_gpio: pmx-uart1-gpio {
337 marvell,pins = "mpp_uart1";
338 marvell,function = "gpio";
339 };
340
341 pmx_nand: pmx-nand {
342 marvell,pins = "mpp_nand";
343 marvell,function = "nand";
344 };
345
346 pmx_nand_gpo: pmx-nand-gpo {
347 marvell,pins = "mpp_nand";
348 marvell,function = "gpo";
349 };
350 };
351
352 spi0: spi-ctrl@10600 {
353 compatible = "marvell,orion-spi";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 cell-index = <0>;
357 interrupts = <6>;
358 reg = <0x10600 0x28>;
359 clocks = <&core_clk 0>;
360 pinctrl-0 = <&pmx_spi0>;
361 pinctrl-names = "default";
362 status = "disabled";
363 };
364
365 spi1: spi-ctrl@14600 {
366 compatible = "marvell,orion-spi";
367 #address-cells = <1>;
368 #size-cells = <0>;
369 cell-index = <1>;
370 interrupts = <5>;
371 reg = <0x14600 0x28>;
372 clocks = <&core_clk 0>;
373 status = "disabled";
374 };
375
376 i2c0: i2c-ctrl@11000 {
377 compatible = "marvell,mv64xxx-i2c";
378 reg = <0x11000 0x20>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 interrupts = <11>;
382 clock-frequency = <400000>;
383 timeout-ms = <1000>;
384 clocks = <&core_clk 0>;
385 status = "disabled";
386 };
387
388 ehci0: usb-host@50000 {
389 compatible = "marvell,orion-ehci";
390 reg = <0x50000 0x1000>;
391 interrupts = <24>;
392 clocks = <&gate_clk 0>;
393 status = "okay";
394 };
395
396 ehci1: usb-host@51000 {
397 compatible = "marvell,orion-ehci";
398 reg = <0x51000 0x1000>;
399 interrupts = <25>;
400 clocks = <&gate_clk 1>;
401 status = "okay";
402 };
403
404 sdio0: sdio-host@92000 {
405 compatible = "marvell,dove-sdhci";
406 reg = <0x92000 0x100>;
407 interrupts = <35>, <37>;
408 clocks = <&gate_clk 8>;
409 pinctrl-0 = <&pmx_sdio0>;
410 pinctrl-names = "default";
411 status = "disabled";
412 };
413
414 sdio1: sdio-host@90000 {
415 compatible = "marvell,dove-sdhci";
416 reg = <0x90000 0x100>;
417 interrupts = <36>, <38>;
418 clocks = <&gate_clk 9>;
419 pinctrl-0 = <&pmx_sdio1>;
420 pinctrl-names = "default";
421 status = "disabled";
422 };
423
424 sata0: sata-host@a0000 {
425 compatible = "marvell,orion-sata";
426 reg = <0xa0000 0x2400>;
427 interrupts = <62>;
428 clocks = <&gate_clk 3>;
429 nr-ports = <1>;
430 status = "disabled";
431 };
432
433 rtc: real-time-clock@d8500 {
434 compatible = "marvell,orion-rtc";
435 reg = <0xd8500 0x20>;
436 };
437
438 crypto: crypto-engine@30000 {
439 compatible = "marvell,orion-crypto";
440 reg = <0x30000 0x10000>,
441 <0xffffe000 0x800>;
442 reg-names = "regs", "sram";
443 interrupts = <31>;
444 clocks = <&gate_clk 15>;
445 status = "okay";
446 };
447
448 xor0: dma-engine@60800 {
449 compatible = "marvell,orion-xor";
450 reg = <0x60800 0x100
451 0x60a00 0x100>;
452 clocks = <&gate_clk 23>;
453 status = "okay";
454
455 channel0 {
456 interrupts = <39>;
457 dmacap,memcpy;
458 dmacap,xor;
459 };
460
461 channel1 {
462 interrupts = <40>;
463 dmacap,memcpy;
464 dmacap,xor;
465 };
466 };
467
468 xor1: dma-engine@60900 {
469 compatible = "marvell,orion-xor";
470 reg = <0x60900 0x100
471 0x60b00 0x100>;
472 clocks = <&gate_clk 24>;
473 status = "okay";
474
475 channel0 {
476 interrupts = <42>;
477 dmacap,memcpy;
478 dmacap,xor;
479 };
480
481 channel1 {
482 interrupts = <43>;
483 dmacap,memcpy;
484 dmacap,xor;
485 };
486 };
487
488 mdio: mdio-bus@72004 {
489 compatible = "marvell,orion-mdio";
490 #address-cells = <1>;
491 #size-cells = <0>;
492 reg = <0x72004 0x84>;
493 interrupts = <30>;
494 clocks = <&gate_clk 2>;
495 status = "disabled";
496
497 ethphy: ethernet-phy {
498 device-type = "ethernet-phy";
499 /* set phy address in board file */
500 };
501 };
502
503 eth: ethernet-ctrl@72000 {
504 compatible = "marvell,orion-eth";
505 #address-cells = <1>;
506 #size-cells = <0>;
507 reg = <0x72000 0x4000>;
508 clocks = <&gate_clk 2>;
509 marvell,tx-checksum-limit = <1600>;
510 status = "disabled";
511
512 ethernet-port@0 {
513 device_type = "network";
514 compatible = "marvell,orion-eth-port";
515 reg = <0>;
516 interrupts = <29>;
517 /* overwrite MAC address in bootloader */
518 local-mac-address = [00 00 00 00 00 00];
519 phy-handle = <&ethphy>;
520 };
528 }; 521 };
529 }; 522 };
530 }; 523 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 04:17:12 -0500