Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson:
 "This is a branch with updates for Marvell's mvebu/kirkwood platforms.
  They came in late-ish, and were heavily interdependent such that it
  didn't make sense to split them up across the cross-platform topic
  branches.  So here they are (for the second release in a row) in a
  branch on their own."

* tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits)
  arm: l2x0: add aurora related properties to OF binding
  arm: mvebu: add Aurora L2 Cache Controller to the DT
  arm: mvebu: add L2 cache support
  dma: mv_xor: fix error handling path
  dma: mv_xor: fix error checking of irq_of_parse_and_map()
  dma: mv_xor: use request_irq() instead of devm_request_irq()
  dma: mv_xor: clear the window override control registers
  arm: mvebu: fix address decoding armada_cfg_base() function
  ARM: mvebu: update defconfig with I2C and RTC support
  ARM: mvebu: Add SATA support for OpenBlocks AX3-4
  ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4
  ARM: mvebu: Add support for I2C on OpenBlocks AX3-4
  ARM: mvebu: Add support for I2C controllers in Armada 370/XP
  arm: mvebu: Add hardware I/O Coherency support
  arm: plat-orion: Add coherency attribute when setup mbus target
  arm: dma mapping: Export a dma ops function arm_dma_set_mask
  arm: mvebu: Add SMP support for Armada XP
  arm: mm: Add support for PJ4B cpu and init routines
  arm: mvebu: Add IPI support via doorbells
  arm: mvebu: Add initial support for power managmement service unit
  ...

1 files changed, 62 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 61f391412a5a..f3f7e9d8adca 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -37,6 +37,19 @@
                         reg = <0x20204 0x04>, <0x20214 0x04>;
                 };
 
+                core_clk: core-clocks@d0214 {
+                        compatible = "marvell,dove-core-clock";
+                        reg = <0xd0214 0x4>;
+                        #clock-cells = <1>;
+                };
+
+                gate_clk: clock-gating-control@d0038 {
+                        compatible = "marvell,dove-gating-clock";
+                        reg = <0xd0038 0x4>;
+                        clocks = <&core_clk 0>;
+                        #clock-cells = <1>;
+                };
+
                 uart0: serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
@@ -113,6 +126,7 @@
                         cell-index = <0>;
                         interrupts = <6>;
                         reg = <0x10600 0x28>;
+                        clocks = <&core_clk 0>;
                         status = "disabled";
                 };
 
@@ -123,6 +137,7 @@
                         cell-index = <1>;
                         interrupts = <5>;
                         reg = <0x14600 0x28>;
+                        clocks = <&core_clk 0>;
                         status = "disabled";
                 };
 
@@ -134,6 +149,7 @@
                         interrupts = <11>;
                         clock-frequency = <400000>;
                         timeout-ms = <1000>;
+                        clocks = <&core_clk 0>;
                         status = "disabled";
                 };
 
@@ -141,6 +157,7 @@
                         compatible = "marvell,dove-sdhci";
                         reg = <0x92000 0x100>;
                         interrupts = <35>, <37>;
+                        clocks = <&gate_clk 8>;
                         status = "disabled";
                 };
 
@@ -148,6 +165,7 @@
                         compatible = "marvell,dove-sdhci";
                         reg = <0x90000 0x100>;
                         interrupts = <36>, <38>;
+                        clocks = <&gate_clk 9>;
                         status = "disabled";
                 };
 
@@ -155,6 +173,7 @@
                         compatible = "marvell,orion-sata";
                         reg = <0xa0000 0x2400>;
                         interrupts = <62>;
+                        clocks = <&gate_clk 3>;
                         nr-ports = <1>;
                         status = "disabled";
                 };
@@ -165,7 +184,50 @@
                               <0xc8000000 0x800>;
                         reg-names = "regs", "sram";
                         interrupts = <31>;
+                        clocks = <&gate_clk 15>;
+                        status = "okay";
+                };
+
+                xor0: dma-engine@60800 {
+                        compatible = "marvell,orion-xor";
+                        reg = <0x60800 0x100
+                               0x60a00 0x100>;
+                        clocks = <&gate_clk 23>;
                         status = "okay";
+
+                        channel0 {
+                                interrupts = <39>;
+                                dmacap,memcpy;
+                                dmacap,xor;
+                        };
+
+                        channel1 {
+                                interrupts = <40>;
+                                dmacap,memset;
+                                dmacap,memcpy;
+                                dmacap,xor;
+                        };
+                };
+
+                xor1: dma-engine@60900 {
+                        compatible = "marvell,orion-xor";
+                        reg = <0x60900 0x100
+                               0x60b00 0x100>;
+                        clocks = <&gate_clk 24>;
+                        status = "okay";
+
+                        channel0 {
+                                interrupts = <42>;
+                                dmacap,memcpy;
+                                dmacap,xor;
+                        };
+
+                        channel1 {
+                                interrupts = <43>;
+                                dmacap,memset;
+                                dmacap,memcpy;
+                                dmacap,xor;
+                        };
                 };
         };
 };