diff options
author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2012-09-24 20:02:16 -0400 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2012-10-17 13:19:55 -0400 |
commit | 138ee960483e90856b6e42613b936433240516ba (patch) | |
tree | 18b19588c9cb44a3674b021c90094604b05dc6de /arch/arm/boot/dts/dove.dtsi | |
parent | 3fbcd3d0a04d8f4ecbe3eb15a407065b86687592 (diff) |
ARM: dove: Restructure SoC device tree descriptor
This patch adds proper ranges for all mapped addresses within
dove SoC and moves the interrupt controller node inside the simple-bus
node.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/dove.dtsi')
-rw-r--r-- | arch/arm/boot/dts/dove.dtsi | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 3f41f503b750..792bab03b577 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi | |||
@@ -4,27 +4,33 @@ | |||
4 | compatible = "marvell,dove"; | 4 | compatible = "marvell,dove"; |
5 | model = "Marvell Armada 88AP510 SoC"; | 5 | model = "Marvell Armada 88AP510 SoC"; |
6 | 6 | ||
7 | interrupt-parent = <&intc>; | 7 | soc@f1000000 { |
8 | |||
9 | intc: interrupt-controller { | ||
10 | compatible = "marvell,orion-intc"; | ||
11 | interrupt-controller; | ||
12 | #interrupt-cells = <1>; | ||
13 | reg = <0xf1020204 0x04>, | ||
14 | <0xf1020214 0x04>; | ||
15 | }; | ||
16 | |||
17 | mbus@f1000000 { | ||
18 | compatible = "simple-bus"; | 8 | compatible = "simple-bus"; |
19 | ranges = <0 0xf1000000 0x4000000>; | ||
20 | #address-cells = <1>; | 9 | #address-cells = <1>; |
21 | #size-cells = <1>; | 10 | #size-cells = <1>; |
11 | interrupt-parent = <&intc>; | ||
12 | |||
13 | ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ | ||
14 | 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ | ||
15 | 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ | ||
16 | 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ | ||
17 | 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ | ||
18 | 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ | ||
19 | 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ | ||
20 | 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ | ||
22 | 21 | ||
23 | l2: l2-cache { | 22 | l2: l2-cache { |
24 | compatible = "marvell,tauros2-cache"; | 23 | compatible = "marvell,tauros2-cache"; |
25 | marvell,tauros2-cache-features = <0>; | 24 | marvell,tauros2-cache-features = <0>; |
26 | }; | 25 | }; |
27 | 26 | ||
27 | intc: interrupt-controller { | ||
28 | compatible = "marvell,orion-intc"; | ||
29 | interrupt-controller; | ||
30 | #interrupt-cells = <1>; | ||
31 | reg = <0x20204 0x04>, <0x20214 0x04>; | ||
32 | }; | ||
33 | |||
28 | uart0: serial@12000 { | 34 | uart0: serial@12000 { |
29 | compatible = "ns16550a"; | 35 | compatible = "ns16550a"; |
30 | reg = <0x12000 0x100>; | 36 | reg = <0x12000 0x100>; |