diff options
author | Christian Daudt <csd@broadcom.com> | 2012-11-19 12:46:10 -0500 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2012-11-20 01:39:07 -0500 |
commit | 8ac49e0485bb79223a111b366a3b1f5ec9148729 (patch) | |
tree | 8846daeeae2c1b70c5e5fe491979c28039054d08 /arch/arm/boot/dts/bcm11351.dtsi | |
parent | 0056a985fab537e161405a48dc8f8da0b47e0767 (diff) |
Add support for generic BCM SoC chipsets
In order to start upstreaming Broadcom SoC support, create
a starting hierarchy, arch and dts files.
The first support SoC family that is planned is the
BCM281XX (BCM11130/11140/11351/28145/28155) family of dual A9 mobile
SoC cores.
This code is just the skeleton code for get the machine upstreamed. It
has been made MULTIPLATFORM compatible.
Next steps
----------
Upstream a basic set of drivers - sufficient for a console boot to
ramdisk. These will includer timer, gpio, i2c drivers.
After this basic set, we will proceed with a more comprehensive set
of drivers for the 281XX SoC family.
v2 patch mods
--------
- Remove l2x0_of_init call as there were problems with the code.
A separate patch will be submitted with cache init code
- Rename capri files and refs to bcm281xx-based names
- Add bcm281xx binding doc
- various misc cleanups
v3 patch mods
-------------
- Remove extra #include lines
- Remove remaining references to capri
- dt uart chipset string added
- cleaned up chip # references
v4 patch mods
-------------
- swap order of compatible definitions for uart
- fix typo
v5 patch mods
-------------
- Rename bcm281xx to bcm11351 in dts+code,
leaving references to bcm281xx only in help+comments.
v6 patch mods
-------------
- fix typo in uart 'compatible' string
Signed-off-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/bcm11351.dtsi')
-rw-r--r-- | arch/arm/boot/dts/bcm11351.dtsi | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi new file mode 100644 index 000000000000..ad135885bd2a --- /dev/null +++ b/arch/arm/boot/dts/bcm11351.dtsi | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Broadcom Corporation | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License as | ||
6 | * published by the Free Software Foundation version 2. | ||
7 | * | ||
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
9 | * kind, whether express or implied; without even the implied warranty | ||
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | */ | ||
13 | |||
14 | /include/ "skeleton.dtsi" | ||
15 | |||
16 | / { | ||
17 | model = "BCM11351 SoC"; | ||
18 | compatible = "bcm,bcm11351"; | ||
19 | interrupt-parent = <&gic>; | ||
20 | |||
21 | chosen { | ||
22 | bootargs = "console=ttyS0,115200n8"; | ||
23 | }; | ||
24 | |||
25 | gic: interrupt-controller@3ff00100 { | ||
26 | compatible = "arm,cortex-a9-gic"; | ||
27 | #interrupt-cells = <3>; | ||
28 | #address-cells = <0>; | ||
29 | interrupt-controller; | ||
30 | reg = <0x3ff01000 0x1000>, | ||
31 | <0x3ff00100 0x100>; | ||
32 | }; | ||
33 | |||
34 | uart@3e000000 { | ||
35 | compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; | ||
36 | status = "disabled"; | ||
37 | reg = <0x3e000000 0x1000>; | ||
38 | clock-frequency = <13000000>; | ||
39 | interrupts = <0x0 67 0x4>; | ||
40 | reg-shift = <2>; | ||
41 | reg-io-width = <4>; | ||
42 | }; | ||
43 | |||
44 | L2: l2-cache { | ||
45 | compatible = "arm,pl310-cache"; | ||
46 | reg = <0x3ff20000 0x1000>; | ||
47 | cache-unified; | ||
48 | cache-level = <2>; | ||
49 | }; | ||
50 | }; | ||