diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2013-04-23 20:34:25 -0400 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-05-17 06:11:39 -0400 |
| commit | c9d0f317c6dc45f84888bc11947bc10e6c547dc3 (patch) | |
| tree | ef4d865a48a66b378917b101c85eb011f5ca624b /arch/arm/boot/dts/at91sam9n12.dtsi | |
| parent | 0e4686e6e662205b87e64af7c0ba9ef81e2c8791 (diff) | |
ARM: at91: dt: switch to pinctrl to pre-processor
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9n12.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/at91sam9n12.dtsi | 89 |
1 files changed, 45 insertions, 44 deletions
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 5205403ca1e3..e166e0c53f5e 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include "skeleton.dtsi" | 10 | #include "skeleton.dtsi" |
| 11 | #include <dt-bindings/pinctrl/at91.h> | ||
| 11 | #include <dt-bindings/gpio/gpio.h> | 12 | #include <dt-bindings/gpio/gpio.h> |
| 12 | 13 | ||
| 13 | / { | 14 | / { |
| @@ -134,152 +135,152 @@ | |||
| 134 | dbgu { | 135 | dbgu { |
| 135 | pinctrl_dbgu: dbgu-0 { | 136 | pinctrl_dbgu: dbgu-0 { |
| 136 | atmel,pins = | 137 | atmel,pins = |
| 137 | <0 9 0x1 0x0 /* PA9 periph A */ | 138 | <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ |
| 138 | 0 10 0x1 0x1>; /* PA10 periph with pullup */ | 139 | AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */ |
| 139 | }; | 140 | }; |
| 140 | }; | 141 | }; |
| 141 | 142 | ||
| 142 | usart0 { | 143 | usart0 { |
| 143 | pinctrl_usart0: usart0-0 { | 144 | pinctrl_usart0: usart0-0 { |
| 144 | atmel,pins = | 145 | atmel,pins = |
| 145 | <0 1 0x1 0x1 /* PA1 periph A with pullup */ | 146 | <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */ |
| 146 | 0 0 0x1 0x0>; /* PA0 periph A */ | 147 | AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */ |
| 147 | }; | 148 | }; |
| 148 | 149 | ||
| 149 | pinctrl_usart0_rts: usart0_rts-0 { | 150 | pinctrl_usart0_rts: usart0_rts-0 { |
| 150 | atmel,pins = | 151 | atmel,pins = |
| 151 | <0 2 0x1 0x0>; /* PA2 periph A */ | 152 | <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */ |
| 152 | }; | 153 | }; |
| 153 | 154 | ||
| 154 | pinctrl_usart0_cts: usart0_cts-0 { | 155 | pinctrl_usart0_cts: usart0_cts-0 { |
| 155 | atmel,pins = | 156 | atmel,pins = |
| 156 | <0 3 0x1 0x0>; /* PA3 periph A */ | 157 | <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */ |
| 157 | }; | 158 | }; |
| 158 | }; | 159 | }; |
| 159 | 160 | ||
| 160 | usart1 { | 161 | usart1 { |
| 161 | pinctrl_usart1: usart1-0 { | 162 | pinctrl_usart1: usart1-0 { |
| 162 | atmel,pins = | 163 | atmel,pins = |
| 163 | <0 6 0x1 0x1 /* PA6 periph A with pullup */ | 164 | <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */ |
| 164 | 0 5 0x1 0x0>; /* PA5 periph A */ | 165 | AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ |
| 165 | }; | 166 | }; |
| 166 | }; | 167 | }; |
| 167 | 168 | ||
| 168 | usart2 { | 169 | usart2 { |
| 169 | pinctrl_usart2: usart2-0 { | 170 | pinctrl_usart2: usart2-0 { |
| 170 | atmel,pins = | 171 | atmel,pins = |
| 171 | <0 8 0x1 0x1 /* PA8 periph A with pullup */ | 172 | <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */ |
| 172 | 0 7 0x1 0x0>; /* PA7 periph A */ | 173 | AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */ |
| 173 | }; | 174 | }; |
| 174 | 175 | ||
| 175 | pinctrl_usart2_rts: usart2_rts-0 { | 176 | pinctrl_usart2_rts: usart2_rts-0 { |
| 176 | atmel,pins = | 177 | atmel,pins = |
| 177 | <1 0 0x2 0x0>; /* PB0 periph B */ | 178 | <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ |
| 178 | }; | 179 | }; |
| 179 | 180 | ||
| 180 | pinctrl_usart2_cts: usart2_cts-0 { | 181 | pinctrl_usart2_cts: usart2_cts-0 { |
| 181 | atmel,pins = | 182 | atmel,pins = |
| 182 | <1 1 0x2 0x0>; /* PB1 periph B */ | 183 | <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ |
| 183 | }; | 184 | }; |
| 184 | }; | 185 | }; |
| 185 | 186 | ||
| 186 | usart3 { | 187 | usart3 { |
| 187 | pinctrl_usart3: usart3-0 { | 188 | pinctrl_usart3: usart3-0 { |
| 188 | atmel,pins = | 189 | atmel,pins = |
| 189 | <2 23 0x2 0x1 /* PC23 periph B with pullup */ | 190 | <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */ |
| 190 | 2 22 0x2 0x0>; /* PC22 periph B */ | 191 | AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */ |
| 191 | }; | 192 | }; |
| 192 | 193 | ||
| 193 | pinctrl_usart3_rts: usart3_rts-0 { | 194 | pinctrl_usart3_rts: usart3_rts-0 { |
| 194 | atmel,pins = | 195 | atmel,pins = |
| 195 | <2 24 0x2 0x0>; /* PC24 periph B */ | 196 | <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */ |
| 196 | }; | 197 | }; |
| 197 | 198 | ||
| 198 | pinctrl_usart3_cts: usart3_cts-0 { | 199 | pinctrl_usart3_cts: usart3_cts-0 { |
| 199 | atmel,pins = | 200 | atmel,pins = |
| 200 | <2 25 0x2 0x0>; /* PC25 periph B */ | 201 | <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */ |
| 201 | }; | 202 | }; |
| 202 | }; | 203 | }; |
| 203 | 204 | ||
| 204 | uart0 { | 205 | uart0 { |
| 205 | pinctrl_uart0: uart0-0 { | 206 | pinctrl_uart0: uart0-0 { |
| 206 | atmel,pins = | 207 | atmel,pins = |
| 207 | <2 9 0x3 0x1 /* PC9 periph C with pullup */ | 208 | <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */ |
| 208 | 2 8 0x3 0x0>; /* PC8 periph C */ | 209 | AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */ |
| 209 | }; | 210 | }; |
| 210 | }; | 211 | }; |
| 211 | 212 | ||
| 212 | uart1 { | 213 | uart1 { |
| 213 | pinctrl_uart1: uart1-0 { | 214 | pinctrl_uart1: uart1-0 { |
| 214 | atmel,pins = | 215 | atmel,pins = |
| 215 | <2 16 0x3 0x1 /* PC17 periph C with pullup */ | 216 | <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */ |
| 216 | 2 17 0x3 0x0>; /* PC16 periph C */ | 217 | AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */ |
| 217 | }; | 218 | }; |
| 218 | }; | 219 | }; |
| 219 | 220 | ||
| 220 | nand { | 221 | nand { |
| 221 | pinctrl_nand: nand-0 { | 222 | pinctrl_nand: nand-0 { |
| 222 | atmel,pins = | 223 | atmel,pins = |
| 223 | <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/ | 224 | <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/ |
| 224 | 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */ | 225 | AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */ |
| 225 | }; | 226 | }; |
| 226 | }; | 227 | }; |
| 227 | 228 | ||
| 228 | mmc0 { | 229 | mmc0 { |
| 229 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | 230 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { |
| 230 | atmel,pins = | 231 | atmel,pins = |
| 231 | <0 17 0x1 0x0 /* PA17 periph A */ | 232 | <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ |
| 232 | 0 16 0x1 0x1 /* PA16 periph A with pullup */ | 233 | AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */ |
| 233 | 0 15 0x1 0x1>; /* PA15 periph A with pullup */ | 234 | AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */ |
| 234 | }; | 235 | }; |
| 235 | 236 | ||
| 236 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | 237 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { |
| 237 | atmel,pins = | 238 | atmel,pins = |
| 238 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | 239 | <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */ |
| 239 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | 240 | AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */ |
| 240 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | 241 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */ |
| 241 | }; | 242 | }; |
| 242 | 243 | ||
| 243 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { | 244 | pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 { |
| 244 | atmel,pins = | 245 | atmel,pins = |
| 245 | <0 11 0x2 0x1 /* PA11 periph B with pullup */ | 246 | <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ |
| 246 | 0 12 0x2 0x1 /* PA12 periph B with pullup */ | 247 | AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */ |
| 247 | 0 13 0x2 0x1 /* PA13 periph B with pullup */ | 248 | AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */ |
| 248 | 0 14 0x2 0x1>; /* PA14 periph B with pullup */ | 249 | AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */ |
| 249 | }; | 250 | }; |
| 250 | }; | 251 | }; |
| 251 | 252 | ||
| 252 | ssc0 { | 253 | ssc0 { |
| 253 | pinctrl_ssc0_tx: ssc0_tx-0 { | 254 | pinctrl_ssc0_tx: ssc0_tx-0 { |
| 254 | atmel,pins = | 255 | atmel,pins = |
| 255 | <0 24 0x2 0x0 /* PA24 periph B */ | 256 | <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ |
| 256 | 0 25 0x2 0x0 /* PA25 periph B */ | 257 | AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ |
| 257 | 0 26 0x2 0x0>; /* PA26 periph B */ | 258 | AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */ |
| 258 | }; | 259 | }; |
| 259 | 260 | ||
| 260 | pinctrl_ssc0_rx: ssc0_rx-0 { | 261 | pinctrl_ssc0_rx: ssc0_rx-0 { |
| 261 | atmel,pins = | 262 | atmel,pins = |
| 262 | <0 27 0x2 0x0 /* PA27 periph B */ | 263 | <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ |
| 263 | 0 28 0x2 0x0 /* PA28 periph B */ | 264 | AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ |
| 264 | 0 29 0x2 0x0>; /* PA29 periph B */ | 265 | AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ |
| 265 | }; | 266 | }; |
| 266 | }; | 267 | }; |
| 267 | 268 | ||
| 268 | spi0 { | 269 | spi0 { |
| 269 | pinctrl_spi0: spi0-0 { | 270 | pinctrl_spi0: spi0-0 { |
| 270 | atmel,pins = | 271 | atmel,pins = |
| 271 | <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */ | 272 | <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */ |
| 272 | 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */ | 273 | AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */ |
| 273 | 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */ | 274 | AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */ |
| 274 | }; | 275 | }; |
| 275 | }; | 276 | }; |
| 276 | 277 | ||
| 277 | spi1 { | 278 | spi1 { |
| 278 | pinctrl_spi1: spi1-0 { | 279 | pinctrl_spi1: spi1-0 { |
| 279 | atmel,pins = | 280 | atmel,pins = |
| 280 | <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */ | 281 | <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */ |
| 281 | 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */ | 282 | AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */ |
| 282 | 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */ | 283 | AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */ |
| 283 | }; | 284 | }; |
| 284 | }; | 285 | }; |
| 285 | 286 | ||