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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-11-18 17:40:01 -0500
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-11-18 17:54:31 -0500
commit9e3129e937e2f178d2a003ea45765e5e63e34665 (patch)
treefab157ec8ba266d60c51823a78848528753bac6b /arch/arm/boot/dts/at91sam9263.dtsi
parentd9b4fe837d671af5329f32570362c3c0b571c40b (diff)
ARM: at91: fix usart/uart namimg in pinctrl
USART are the full pin uart DBGU the debug Unit UART the two pin uart Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9263.dtsi')
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 148b89a50eed..cf4b59fc8e08 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -113,42 +113,42 @@
113 }; 113 };
114 }; 114 };
115 115
116 uart0 { 116 usart0 {
117 pinctrl_uart0: uart0-0 { 117 pinctrl_usart0: usart0-0 {
118 atmel,pins = 118 atmel,pins =
119 <0 26 0x1 0x1 /* PA26 periph A with pullup */ 119 <0 26 0x1 0x1 /* PA26 periph A with pullup */
120 0 27 0x1 0x0>; /* PA27 periph A */ 120 0 27 0x1 0x0>; /* PA27 periph A */
121 }; 121 };
122 122
123 pinctrl_uart0_rts_cts: uart0_rts_cts-0 { 123 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
124 atmel,pins = 124 atmel,pins =
125 <0 28 0x1 0x0 /* PA28 periph A */ 125 <0 28 0x1 0x0 /* PA28 periph A */
126 0 29 0x1 0x0>; /* PA29 periph A */ 126 0 29 0x1 0x0>; /* PA29 periph A */
127 }; 127 };
128 }; 128 };
129 129
130 uart1 { 130 usart1 {
131 pinctrl_uart1: uart1-0 { 131 pinctrl_usart1: usart1-0 {
132 atmel,pins = 132 atmel,pins =
133 <3 0 0x1 0x1 /* PD0 periph A with pullup */ 133 <3 0 0x1 0x1 /* PD0 periph A with pullup */
134 3 1 0x1 0x0>; /* PD1 periph A */ 134 3 1 0x1 0x0>; /* PD1 periph A */
135 }; 135 };
136 136
137 pinctrl_uart1_rts_cts: uart1_rts_cts-0 { 137 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
138 atmel,pins = 138 atmel,pins =
139 <3 7 0x2 0x0 /* PD7 periph B */ 139 <3 7 0x2 0x0 /* PD7 periph B */
140 3 8 0x2 0x0>; /* PD8 periph B */ 140 3 8 0x2 0x0>; /* PD8 periph B */
141 }; 141 };
142 }; 142 };
143 143
144 uart2 { 144 usart2 {
145 pinctrl_uart2: uart2-0 { 145 pinctrl_usart2: usart2-0 {
146 atmel,pins = 146 atmel,pins =
147 <3 2 0x1 0x1 /* PD2 periph A with pullup */ 147 <3 2 0x1 0x1 /* PD2 periph A with pullup */
148 3 3 0x1 0x0>; /* PD3 periph A */ 148 3 3 0x1 0x0>; /* PD3 periph A */
149 }; 149 };
150 150
151 pinctrl_uart2_rts_cts: uart2_rts_cts-0 { 151 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
152 atmel,pins = 152 atmel,pins =
153 <3 5 0x2 0x0 /* PD5 periph B */ 153 <3 5 0x2 0x0 /* PD5 periph B */
154 4 6 0x2 0x0>; /* PD6 periph B */ 154 4 6 0x2 0x0>; /* PD6 periph B */
@@ -258,7 +258,7 @@
258 atmel,use-dma-rx; 258 atmel,use-dma-rx;
259 atmel,use-dma-tx; 259 atmel,use-dma-tx;
260 pinctrl-names = "default"; 260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_uart0>; 261 pinctrl-0 = <&pinctrl_usart0>;
262 status = "disabled"; 262 status = "disabled";
263 }; 263 };
264 264
@@ -269,7 +269,7 @@
269 atmel,use-dma-rx; 269 atmel,use-dma-rx;
270 atmel,use-dma-tx; 270 atmel,use-dma-tx;
271 pinctrl-names = "default"; 271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_uart1>; 272 pinctrl-0 = <&pinctrl_usart1>;
273 status = "disabled"; 273 status = "disabled";
274 }; 274 };
275 275
@@ -280,7 +280,7 @@
280 atmel,use-dma-rx; 280 atmel,use-dma-rx;
281 atmel,use-dma-tx; 281 atmel,use-dma-tx;
282 pinctrl-names = "default"; 282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_uart2>; 283 pinctrl-0 = <&pinctrl_usart2>;
284 status = "disabled"; 284 status = "disabled";
285 }; 285 };
286 286