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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2014-04-23 04:53:39 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-05-12 10:48:51 -0400
commit32da8c850247f90d9f0bb4efc3729404d9d7436a (patch)
tree71577fb9dc684d5b175c0d2c53783520c5415eb5 /arch/arm/boot/dts/at91sam9261.dtsi
parentb1059186299df841a8774b5cd76bdd06dbc566f3 (diff)
ARM: at91/dt: sam9261: Add ssc2, SSC clocks and pcks
Add ssc2 support, ssc2 pinctrl and clocks for the three SSCs. Also add support for the programmable clocks. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9261.dtsi')
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi103
1 files changed, 103 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 81f22476b024..10083c236cbe 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -29,6 +29,7 @@
29 i2c0 = &i2c0; 29 i2c0 = &i2c0;
30 ssc0 = &ssc0; 30 ssc0 = &ssc0;
31 ssc1 = &ssc1; 31 ssc1 = &ssc1;
32 ssc2 = &ssc2;
32 }; 33 };
33 34
34 cpus { 35 cpus {
@@ -182,6 +183,8 @@
182 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 183 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
183 pinctrl-names = "default"; 184 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 185 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
186 clocks = <&ssc0_clk>;
187 clock-names = "pclk";
185 status = "disabled"; 188 status = "disabled";
186 }; 189 };
187 190
@@ -191,6 +194,19 @@
191 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 194 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
192 pinctrl-names = "default"; 195 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 196 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
197 clocks = <&ssc1_clk>;
198 clock-names = "pclk";
199 status = "disabled";
200 };
201
202 ssc2: ssc@fffc4000 {
203 compatible = "atmel,at91rm9200-ssc";
204 reg = <0xfffc4000 0x4000>;
205 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
208 clocks = <&ssc2_clk>;
209 clock-names = "pclk";
194 status = "disabled"; 210 status = "disabled";
195 }; 211 };
196 212
@@ -385,6 +401,22 @@
385 }; 401 };
386 }; 402 };
387 403
404 ssc2 {
405 pinctrl_ssc2_tx: ssc2_tx-0 {
406 atmel,pins =
407 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
408 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
409 <AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
410 };
411
412 pinctrl_ssc2_rx: ssc2_rx-0 {
413 atmel,pins =
414 <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
415 <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
416 <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
417 };
418 };
419
388 spi0 { 420 spi0 {
389 pinctrl_spi0: spi0-0 { 421 pinctrl_spi0: spi0-0 {
390 atmel,pins = 422 atmel,pins =
@@ -576,6 +608,38 @@
576 clocks = <&pllb>; 608 clocks = <&pllb>;
577 }; 609 };
578 610
611 prog: progck {
612 compatible = "atmel,at91rm9200-clk-programmable";
613 #address-cells = <1>;
614 #size-cells = <0>;
615 interrupt-parent = <&pmc>;
616 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
617
618 prog0: prog0 {
619 #clock-cells = <0>;
620 reg = <0>;
621 interrupts = <AT91_PMC_PCKRDY(0)>;
622 };
623
624 prog1: prog1 {
625 #clock-cells = <0>;
626 reg = <1>;
627 interrupts = <AT91_PMC_PCKRDY(1)>;
628 };
629
630 prog2: prog2 {
631 #clock-cells = <0>;
632 reg = <2>;
633 interrupts = <AT91_PMC_PCKRDY(2)>;
634 };
635
636 prog3: prog3 {
637 #clock-cells = <0>;
638 reg = <3>;
639 interrupts = <AT91_PMC_PCKRDY(3)>;
640 };
641 };
642
579 systemck { 643 systemck {
580 compatible = "atmel,at91rm9200-clk-system"; 644 compatible = "atmel,at91rm9200-clk-system";
581 #address-cells = <1>; 645 #address-cells = <1>;
@@ -593,6 +657,30 @@
593 clocks = <&usb>; 657 clocks = <&usb>;
594 }; 658 };
595 659
660 pck0: pck0 {
661 #clock-cells = <0>;
662 reg = <8>;
663 clocks = <&prog0>;
664 };
665
666 pck1: pck1 {
667 #clock-cells = <0>;
668 reg = <9>;
669 clocks = <&prog1>;
670 };
671
672 pck2: pck2 {
673 #clock-cells = <0>;
674 reg = <10>;
675 clocks = <&prog2>;
676 };
677
678 pck3: pck3 {
679 #clock-cells = <0>;
680 reg = <11>;
681 clocks = <&prog3>;
682 };
683
596 hclk0: hclk0 { 684 hclk0: hclk0 {
597 #clock-cells = <0>; 685 #clock-cells = <0>;
598 reg = <16>; 686 reg = <16>;
@@ -667,6 +755,21 @@
667 reg = <13>; 755 reg = <13>;
668 }; 756 };
669 757
758 ssc0_clk: ssc0_clk {
759 #clock-cells = <0>;
760 reg = <14>;
761 };
762
763 ssc1_clk: ssc1_clk {
764 #clock-cells = <0>;
765 reg = <15>;
766 };
767
768 ssc2_clk: ssc2_clk {
769 #clock-cells = <0>;
770 reg = <16>;
771 };
772
670 tc0_clk: tc0_clk { 773 tc0_clk: tc0_clk {
671 #clock-cells = <0>; 774 #clock-cells = <0>;
672 reg = <17>; 775 reg = <17>;