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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-11-18 17:40:01 -0500
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-11-18 17:54:31 -0500
commit9e3129e937e2f178d2a003ea45765e5e63e34665 (patch)
treefab157ec8ba266d60c51823a78848528753bac6b /arch/arm/boot/dts/at91sam9260.dtsi
parentd9b4fe837d671af5329f32570362c3c0b571c40b (diff)
ARM: at91: fix usart/uart namimg in pinctrl
USART are the full pin uart DBGU the debug Unit UART the two pin uart Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9260.dtsi')
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi58
1 files changed, 29 insertions, 29 deletions
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 36f55e34a430..40bf3298c7fe 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -21,8 +21,8 @@
21 serial2 = &usart1; 21 serial2 = &usart1;
22 serial3 = &usart2; 22 serial3 = &usart2;
23 serial4 = &usart3; 23 serial4 = &usart3;
24 serial5 = &usart4; 24 serial5 = &uart0;
25 serial6 = &usart5; 25 serial6 = &uart1;
26 gpio0 = &pioA; 26 gpio0 = &pioA;
27 gpio1 = &pioB; 27 gpio1 = &pioB;
28 gpio2 = &pioC; 28 gpio2 = &pioC;
@@ -120,88 +120,88 @@
120 }; 120 };
121 }; 121 };
122 122
123 uart0 { 123 usart0 {
124 pinctrl_uart0: uart0-0 { 124 pinctrl_usart0: usart0-0 {
125 atmel,pins = 125 atmel,pins =
126 <1 4 0x1 0x0 /* PB4 periph A */ 126 <1 4 0x1 0x0 /* PB4 periph A */
127 1 5 0x1 0x0>; /* PB5 periph A */ 127 1 5 0x1 0x0>; /* PB5 periph A */
128 }; 128 };
129 129
130 pinctrl_uart0_rts_cts: uart0_rts_cts-0 { 130 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
131 atmel,pins = 131 atmel,pins =
132 <1 26 0x1 0x0 /* PB26 periph A */ 132 <1 26 0x1 0x0 /* PB26 periph A */
133 1 27 0x1 0x0>; /* PB27 periph A */ 133 1 27 0x1 0x0>; /* PB27 periph A */
134 }; 134 };
135 135
136 pinctrl_uart0_dtr_dsr: uart0_dtr_dsr-0 { 136 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
137 atmel,pins = 137 atmel,pins =
138 <1 24 0x1 0x0 /* PB24 periph A */ 138 <1 24 0x1 0x0 /* PB24 periph A */
139 1 22 0x1 0x0>; /* PB22 periph A */ 139 1 22 0x1 0x0>; /* PB22 periph A */
140 }; 140 };
141 141
142 pinctrl_uart0_dcd: uart0_dcd-0 { 142 pinctrl_usart0_dcd: usart0_dcd-0 {
143 atmel,pins = 143 atmel,pins =
144 <1 23 0x1 0x0>; /* PB23 periph A */ 144 <1 23 0x1 0x0>; /* PB23 periph A */
145 }; 145 };
146 146
147 pinctrl_uart0_ri: uart0_ri-0 { 147 pinctrl_usart0_ri: usart0_ri-0 {
148 atmel,pins = 148 atmel,pins =
149 <1 25 0x1 0x0>; /* PB25 periph A */ 149 <1 25 0x1 0x0>; /* PB25 periph A */
150 }; 150 };
151 }; 151 };
152 152
153 uart1 { 153 usart1 {
154 pinctrl_uart1: uart1-0 { 154 pinctrl_usart1: usart1-0 {
155 atmel,pins = 155 atmel,pins =
156 <2 6 0x1 0x1 /* PB6 periph A with pullup */ 156 <2 6 0x1 0x1 /* PB6 periph A with pullup */
157 2 7 0x1 0x0>; /* PB7 periph A */ 157 2 7 0x1 0x0>; /* PB7 periph A */
158 }; 158 };
159 159
160 pinctrl_uart1_rts_cts: uart1_rts_cts-0 { 160 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
161 atmel,pins = 161 atmel,pins =
162 <1 28 0x1 0x0 /* PB28 periph A */ 162 <1 28 0x1 0x0 /* PB28 periph A */
163 1 29 0x1 0x0>; /* PB29 periph A */ 163 1 29 0x1 0x0>; /* PB29 periph A */
164 }; 164 };
165 }; 165 };
166 166
167 uart2 { 167 usart2 {
168 pinctrl_uart2: uart2-0 { 168 pinctrl_usart2: usart2-0 {
169 atmel,pins = 169 atmel,pins =
170 <1 8 0x1 0x1 /* PB8 periph A with pullup */ 170 <1 8 0x1 0x1 /* PB8 periph A with pullup */
171 1 9 0x1 0x0>; /* PB9 periph A */ 171 1 9 0x1 0x0>; /* PB9 periph A */
172 }; 172 };
173 173
174 pinctrl_uart2_rts_cts: uart2_rts_cts-0 { 174 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
175 atmel,pins = 175 atmel,pins =
176 <0 4 0x1 0x0 /* PA4 periph A */ 176 <0 4 0x1 0x0 /* PA4 periph A */
177 0 5 0x1 0x0>; /* PA5 periph A */ 177 0 5 0x1 0x0>; /* PA5 periph A */
178 }; 178 };
179 }; 179 };
180 180
181 uart3 { 181 usart3 {
182 pinctrl_uart3: uart3-0 { 182 pinctrl_usart3: usart3-0 {
183 atmel,pins = 183 atmel,pins =
184 <2 10 0x1 0x1 /* PB10 periph A with pullup */ 184 <2 10 0x1 0x1 /* PB10 periph A with pullup */
185 2 11 0x1 0x0>; /* PB11 periph A */ 185 2 11 0x1 0x0>; /* PB11 periph A */
186 }; 186 };
187 187
188 pinctrl_uart3_rts_cts: uart3_rts_cts-0 { 188 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
189 atmel,pins = 189 atmel,pins =
190 <3 8 0x2 0x0 /* PB8 periph B */ 190 <3 8 0x2 0x0 /* PB8 periph B */
191 3 10 0x2 0x0>; /* PB10 periph B */ 191 3 10 0x2 0x0>; /* PB10 periph B */
192 }; 192 };
193 }; 193 };
194 194
195 uart4 { 195 uart0 {
196 pinctrl_uart4: uart4-0 { 196 pinctrl_uart0: uart0-0 {
197 atmel,pins = 197 atmel,pins =
198 <0 31 0x2 0x1 /* PA31 periph B with pullup */ 198 <0 31 0x2 0x1 /* PA31 periph B with pullup */
199 0 30 0x2 0x0>; /* PA30 periph B */ 199 0 30 0x2 0x0>; /* PA30 periph B */
200 }; 200 };
201 }; 201 };
202 202
203 uart5 { 203 uart1 {
204 pinctrl_uart5: uart5-0 { 204 pinctrl_uart1: uart1-0 {
205 atmel,pins = 205 atmel,pins =
206 <2 12 0x1 0x1 /* PB12 periph A with pullup */ 206 <2 12 0x1 0x1 /* PB12 periph A with pullup */
207 2 13 0x1 0x0>; /* PB13 periph A */ 207 2 13 0x1 0x0>; /* PB13 periph A */
@@ -303,7 +303,7 @@
303 atmel,use-dma-rx; 303 atmel,use-dma-rx;
304 atmel,use-dma-tx; 304 atmel,use-dma-tx;
305 pinctrl-names = "default"; 305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_uart0>; 306 pinctrl-0 = <&pinctrl_usart0>;
307 status = "disabled"; 307 status = "disabled";
308 }; 308 };
309 309
@@ -314,7 +314,7 @@
314 atmel,use-dma-rx; 314 atmel,use-dma-rx;
315 atmel,use-dma-tx; 315 atmel,use-dma-tx;
316 pinctrl-names = "default"; 316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_uart1>; 317 pinctrl-0 = <&pinctrl_usart1>;
318 status = "disabled"; 318 status = "disabled";
319 }; 319 };
320 320
@@ -325,7 +325,7 @@
325 atmel,use-dma-rx; 325 atmel,use-dma-rx;
326 atmel,use-dma-tx; 326 atmel,use-dma-tx;
327 pinctrl-names = "default"; 327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_uart2>; 328 pinctrl-0 = <&pinctrl_usart2>;
329 status = "disabled"; 329 status = "disabled";
330 }; 330 };
331 331
@@ -336,29 +336,29 @@
336 atmel,use-dma-rx; 336 atmel,use-dma-rx;
337 atmel,use-dma-tx; 337 atmel,use-dma-tx;
338 pinctrl-names = "default"; 338 pinctrl-names = "default";
339 pinctrl-0 = <&pinctrl_uart3>; 339 pinctrl-0 = <&pinctrl_usart3>;
340 status = "disabled"; 340 status = "disabled";
341 }; 341 };
342 342
343 usart4: serial@fffd4000 { 343 uart0: serial@fffd4000 {
344 compatible = "atmel,at91sam9260-usart"; 344 compatible = "atmel,at91sam9260-usart";
345 reg = <0xfffd4000 0x200>; 345 reg = <0xfffd4000 0x200>;
346 interrupts = <24 4 5>; 346 interrupts = <24 4 5>;
347 atmel,use-dma-rx; 347 atmel,use-dma-rx;
348 atmel,use-dma-tx; 348 atmel,use-dma-tx;
349 pinctrl-names = "default"; 349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_uart4>; 350 pinctrl-0 = <&pinctrl_uart0>;
351 status = "disabled"; 351 status = "disabled";
352 }; 352 };
353 353
354 usart5: serial@fffd8000 { 354 uart1: serial@fffd8000 {
355 compatible = "atmel,at91sam9260-usart"; 355 compatible = "atmel,at91sam9260-usart";
356 reg = <0xfffd8000 0x200>; 356 reg = <0xfffd8000 0x200>;
357 interrupts = <25 4 5>; 357 interrupts = <25 4 5>;
358 atmel,use-dma-rx; 358 atmel,use-dma-rx;
359 atmel,use-dma-tx; 359 atmel,use-dma-tx;
360 pinctrl-names = "default"; 360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_uart5>; 361 pinctrl-0 = <&pinctrl_uart1>;
362 status = "disabled"; 362 status = "disabled";
363 }; 363 };
364 364