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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-11-18 18:30:01 -0500
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2012-11-18 18:50:56 -0500
commitc58c0c5acceb8acd3d447483a744e8a4a7c27f26 (patch)
tree0eaf3cf08eab1ca4d26bd6755b2ad74e601561c6 /arch/arm/boot/dts/at91sam9260.dtsi
parent9e3129e937e2f178d2a003ea45765e5e63e34665 (diff)
ARM: at91: dt: at91sam9260: split rts and cts pinctrl not
as we just use the rts and not the rts & cts for rs485 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch/arm/boot/dts/at91sam9260.dtsi')
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi40
1 files changed, 28 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 40bf3298c7fe..a5d94606e15d 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -127,10 +127,14 @@
127 1 5 0x1 0x0>; /* PB5 periph A */ 127 1 5 0x1 0x0>; /* PB5 periph A */
128 }; 128 };
129 129
130 pinctrl_usart0_rts_cts: usart0_rts_cts-0 { 130 pinctrl_usart0_rts: usart0_rts-0 {
131 atmel,pins = 131 atmel,pins =
132 <1 26 0x1 0x0 /* PB26 periph A */ 132 <1 26 0x1 0x0>; /* PB26 periph A */
133 1 27 0x1 0x0>; /* PB27 periph A */ 133 };
134
135 pinctrl_usart0_cts: usart0_cts-0 {
136 atmel,pins =
137 <1 27 0x1 0x0>; /* PB27 periph A */
134 }; 138 };
135 139
136 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { 140 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
@@ -157,10 +161,14 @@
157 2 7 0x1 0x0>; /* PB7 periph A */ 161 2 7 0x1 0x0>; /* PB7 periph A */
158 }; 162 };
159 163
160 pinctrl_usart1_rts_cts: usart1_rts_cts-0 { 164 pinctrl_usart1_rts: usart1_rts-0 {
165 atmel,pins =
166 <1 28 0x1 0x0>; /* PB28 periph A */
167 };
168
169 pinctrl_usart1_cts: usart1_cts-0 {
161 atmel,pins = 170 atmel,pins =
162 <1 28 0x1 0x0 /* PB28 periph A */ 171 <1 29 0x1 0x0>; /* PB29 periph A */
163 1 29 0x1 0x0>; /* PB29 periph A */
164 }; 172 };
165 }; 173 };
166 174
@@ -171,10 +179,14 @@
171 1 9 0x1 0x0>; /* PB9 periph A */ 179 1 9 0x1 0x0>; /* PB9 periph A */
172 }; 180 };
173 181
174 pinctrl_usart2_rts_cts: usart2_rts_cts-0 { 182 pinctrl_usart2_rts: usart2_rts-0 {
175 atmel,pins = 183 atmel,pins =
176 <0 4 0x1 0x0 /* PA4 periph A */ 184 <0 4 0x1 0x0>; /* PA4 periph A */
177 0 5 0x1 0x0>; /* PA5 periph A */ 185 };
186
187 pinctrl_usart2_cts: usart2_cts-0 {
188 atmel,pins =
189 <0 5 0x1 0x0>; /* PA5 periph A */
178 }; 190 };
179 }; 191 };
180 192
@@ -185,10 +197,14 @@
185 2 11 0x1 0x0>; /* PB11 periph A */ 197 2 11 0x1 0x0>; /* PB11 periph A */
186 }; 198 };
187 199
188 pinctrl_usart3_rts_cts: usart3_rts_cts-0 { 200 pinctrl_usart3_rts: usart3_rts-0 {
201 atmel,pins =
202 <3 8 0x2 0x0>; /* PB8 periph B */
203 };
204
205 pinctrl_usart3_cts: usart3_cts-0 {
189 atmel,pins = 206 atmel,pins =
190 <3 8 0x2 0x0 /* PB8 periph B */ 207 <3 10 0x2 0x0>; /* PB10 periph B */
191 3 10 0x2 0x0>; /* PB10 periph B */
192 }; 208 };
193 }; 209 };
194 210