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authorMugunthan V N <mugunthanvnm@ti.com>2013-06-07 07:32:54 -0400
committerBenoit Cousson <benoit.cousson@linaro.org>2013-06-19 05:49:40 -0400
commit50c7d2bdd149d4d684b91ca85dd57fc55339e111 (patch)
tree39e9ebf7f8bcdbcb4f1c66acf17d43f6d067f684 /arch/arm/boot/dts/am335x-evm.dts
parent94a924ca61f05e444a3f7b860b2720d81b391da6 (diff)
ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Sleep mode is nothing but the values required for the module during inactive state. The pins are configured to its reset state to optimize energy usage for the pins for the suspend/resume cycle Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/am335x-evm.dts')
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts64
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index a150d0441b5e..a16bb9691cc6 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -97,6 +97,58 @@
97 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 97 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
98 >; 98 >;
99 }; 99 };
100
101 cpsw_default: cpsw_default {
102 pinctrl-single,pins = <
103 /* Slave 1 */
104 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
105 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
106 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
107 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
108 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
109 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
110 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
111 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
112 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
113 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
114 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
115 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
116 >;
117 };
118
119 cpsw_sleep: cpsw_sleep {
120 pinctrl-single,pins = <
121 /* Slave 1 reset value */
122 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 >;
135 };
136
137 davinci_mdio_default: davinci_mdio_default {
138 pinctrl-single,pins = <
139 /* MDIO */
140 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
141 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
142 >;
143 };
144
145 davinci_mdio_sleep: davinci_mdio_sleep {
146 pinctrl-single,pins = <
147 /* MDIO reset value */
148 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
149 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 >;
151 };
100 }; 152 };
101 153
102 ocp { 154 ocp {
@@ -401,6 +453,18 @@
401 }; 453 };
402}; 454};
403 455
456&mac {
457 pinctrl-names = "default", "sleep";
458 pinctrl-0 = <&cpsw_default>;
459 pinctrl-1 = <&cpsw_sleep>;
460};
461
462&davinci_mdio {
463 pinctrl-names = "default", "sleep";
464 pinctrl-0 = <&davinci_mdio_default>;
465 pinctrl-1 = <&davinci_mdio_sleep>;
466};
467
404&cpsw_emac0 { 468&cpsw_emac0 {
405 phy_id = <&davinci_mdio>, <0>; 469 phy_id = <&davinci_mdio>, <0>;
406}; 470};