Merge branch 'orion' into devel

* orion: (26 commits)
  [ARM] Orion: implement power-off method for QNAP TS-109/209
  [ARM] Orion: add support for QNAP TS-109/TS-209
  [ARM] Orion: I2C support
  [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries
  [I2C] Split mv643xx I2C platform support
  [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323
  [ARM] Orion defconfig
  [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323
  [ARM] Orion: MV88F5181 support bits
  [ARM] Orion: Buffalo/Revogear Kurobox Pro support
  [ARM] OrionNAS RD board support
  [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board
  [ARM] Orion: common platform setup for Gigabit Ethernet port
  [ARM] Orion: platform device registration for UART, USB and NAND
  [ARM] Orion: system timer support
  [ARM] Orion edge GPIO IRQ support
  [ARM] Orion: IRQ support
  [ARM] Orion: provide GPIO method for enabling hardware assisted blinking
  [ARM] Orion: GPIO support
  [ARM] Orion: programable address map support
  ...

Conflicts:

	arch/arm/Kconfig
	arch/arm/Makefile

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 14 insertions, 1 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 5cac46a19bb7..3c2c8f2a1dc4 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -623,6 +623,12 @@ proc_types:
                 b       __armv4_mmu_cache_off
                 b       __armv4_mmu_cache_flush
 
+                .word   0x56055310              @ Feroceon
+                .word   0xfffffff0
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv5tej_mmu_cache_flush
+
                 @ These match on the architecture ID
 
                 .word   0x00020000              @ ARMv4T
@@ -641,7 +647,7 @@ proc_types:
                 .word   0x000f0000
                 b       __armv4_mmu_cache_on
                 b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                b       __armv5tej_mmu_cache_flush
 
                 .word   0x0007b000              @ ARMv6
                 .word   0x000ff000
@@ -821,6 +827,13 @@ iflush:
                 mcr     p15, 0, r10, c7, c10, 4 @ drain WB
                 mov     pc, lr
 
+__armv5tej_mmu_cache_flush:
+1:              mrc     p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
+                bne     1b
+                mcr     p15, 0, r0, c7, c5, 0   @ flush I cache
+                mcr     p15, 0, r0, c7, c10, 4  @ drain WB
+                mov     pc, lr
+
 __armv4_mmu_cache_flush:
                 mov     r2, #64*1024            @ default: 32K dcache size (*2)
                 mov     r11, #32                @ default: 32 byte line size