[ARM] nommu: manage the CP15 things

All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 75df1f764a10..e5ab51b9cceb 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -82,9 +82,11 @@
                 kphex   r6, 8           /* processor id */
                 kputc   #':'
                 kphex   r7, 8           /* architecture id */
+#ifdef CONFIG_CPU_CP15
                 kputc   #':'
                 mrc     p15, 0, r0, c1, c0
                 kphex   r0, 8           /* control reg */
+#endif
                 kputc   #'\n'
                 kphex   r5, 8           /* decompressed kernel start */
                 kputc   #'-'
@@ -507,7 +509,11 @@ call_kernel:	bl	cache_clean_flush
  */
 
 call_cache_fn:  adr     r12, proc_types
+#ifdef CONFIG_CPU_CP15
                 mrc     p15, 0, r6, c0, c0      @ get processor ID
+#else
+                ldr     r6, =CONFIG_PROCESSOR_ID
+#endif
 1:              ldr     r1, [r12, #0]           @ get value
                 ldr     r2, [r12, #4]           @ get mask
                 eor     r1, r1, r6              @ (real ^ match)