[ARM] 3541/2: workaround for PXA27x erratum E7

Patch from Nicolas Pitre

According to the Intel PXA27x Processor Family Specification
Update document (doc.nr. 280071-009) erratum E7, some care must be taken
to locate the disabling and re-enabling of the MMU to the beginning of a
cache line to avoid problems in some circumstances.

Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this
up.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 2 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 23016f6aa645..9b42b88bfba0 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -448,8 +448,11 @@ __common_mmu_cache_on:
                 mov     r1, #-1
                 mcr     p15, 0, r3, c2, c0, 0   @ load page table pointer
                 mcr     p15, 0, r1, c3, c0, 0   @ load domain access control
-                mcr     p15, 0, r0, c1, c0, 0   @ load control register
-                mov     pc, lr
+                b       1f
+                .align  5                       @ cache line aligned
+1:              mcr     p15, 0, r0, c1, c0, 0   @ load control register
+                mrc     p15, 0, r0, c1, c0, 0   @ and read it back to
+                sub     pc, lr, r0, lsr #32     @ properly flush pipeline
 
 /*
  * All code following this line is relocatable.  It is relocated by