Merge branch 'imx-features-for-arnd' of git://git.pengutronix.de/git/imx/linux-2.6 into imx/devel

Conflicts:
	arch/arm/mach-mx5/clock-mx51-mx53.c
	arch/arm/mach-mx5/devices-imx53.h

1 files changed, 26 insertions, 0 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 975b5ddc60e9..3bf38c84fd23 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1272,6 +1272,32 @@ config ARM_ERRATA_754327
           This workaround defines cpu_relax() as smp_mb(), preventing correctly
           written polling loops from denying visibility of updates to memory.
 
+config ARM_ERRATA_364296
+        bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
+        depends on CPU_V6 && !SMP
+        help
+          This options enables the workaround for the 364296 ARM1136
+          r0p2 erratum (possible cache data corruption with
+          hit-under-miss enabled). It sets the undocumented bit 31 in
+          the auxiliary control register and the FI bit in the control
+          register, thus disabling hit-under-miss without putting the
+          processor into full low interrupt latency mode. ARM11MPCore
+          is not affected.
+
+config ARM_ERRATA_764369
+        bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for erratum 764369
+          affecting Cortex-A9 MPCore with two or more processors (all
+          current revisions). Under certain timing circumstances, a data
+          cache line maintenance operation by MVA targeting an Inner
+          Shareable memory region may fail to proceed up to either the
+          Point of Coherency or to the Point of Unification of the
+          system. This workaround adds a DSB instruction before the
+          relevant cache maintenance functions and sets a specific bit
+          in the diagnostic control register of the SCU.
+
 endmenu
 
 source "arch/arm/common/Kconfig"