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authorGregory CLEMENT <gregory.clement@free-electrons.com>2013-06-23 05:17:11 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-06-24 09:28:46 -0400
commit3e0a07f8c401bb43e0f964c5f1285b2cb2028645 (patch)
tree8d25c87e417d999d33f621cf74371df5d6751c66 /arch/arm/Kconfig
parent63384fd0b1509acf522a8a8fcede09087eedb7df (diff)
ARM: 7773/1: PJ4B: Add support for errata 4742
This commit fixes the regression on Armada 370 (the kernal hang during boot) introduced by the commit: "ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead". When coming out of either a Wait for Interrupt (WFI) or a Wait for Event (WFE) IDLE states, a specific timing sensitivity exists between the retiring WFI/WFE instructions and the newly issued subsequent instructions. This sensitivity can result in a CPU hang scenario. The workaround is to insert either a Data Synchronization Barrier (DSB) or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction. This commit was based on the work of Lior Amsalem, but heavily modified to apply the errata fix dynamically according to the processor type thanks to the suggestions of Russell King and Nicolas Pitre. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Willy Tarreau <w@1wt.eu> Cc: <stable@vger.kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2651b1da1c56..136f263ed47b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1087,6 +1087,20 @@ if !MMU
1087source "arch/arm/Kconfig-nommu" 1087source "arch/arm/Kconfig-nommu"
1088endif 1088endif
1089 1089
1090config PJ4B_ERRATA_4742
1091 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1092 depends on CPU_PJ4B && MACH_ARMADA_370
1093 default y
1094 help
1095 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1096 Event (WFE) IDLE states, a specific timing sensitivity exists between
1097 the retiring WFI/WFE instructions and the newly issued subsequent
1098 instructions. This sensitivity can result in a CPU hang scenario.
1099 Workaround:
1100 The software must insert either a Data Synchronization Barrier (DSB)
1101 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1102 instruction
1103
1090config ARM_ERRATA_326103 1104config ARM_ERRATA_326103
1091 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1105 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1092 depends on CPU_V6 1106 depends on CPU_V6