Merge remote branch 'rmk/for-linus' into for-linus

* rmk/for-linus: (1557 commits)
  ARM: 6806/1: irq: introduce entry and exit functions for chained handlers
  ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas
  ARM: 6747/1: P2V: Thumb2 support
  ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump
  ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode
  ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9
  ARM: 6772/1: errata: possible fault MMU translations following an ASID switch
  ARM: 6776/1: mach-ux500: activate fix for errata 753970
  ARM: 6794/1: SPEAr: Append UL to device address macros.
  ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files
  ARM: 6792/1: SPEAr: Replace SIZE macro's with SZ_4K macros
  ARM: 6791/1: SPEAr3xx: Declare device structures after shirq code
  ARM: 6790/1: SPEAr: Clock Framework: Rename usbd clock and align apb_clk entry
  ARM: 6789/1: SPEAr3xx: Rename sdio to sdhci
  ARM: 6788/1: SPEAr: Include mach/hardware.h instead of mach/spear.h
  ARM: 6787/1: SPEAr: Reorder #includes in .h & .c files.
  ARM: 6681/1: SPEAr: add debugfs support to clk API
  ARM: 6703/1: SPEAr: update clk API support
  ARM: 6679/1: SPEAr: make clk API functions more generic
  ARM: 6737/1: SPEAr: formalized timer support
  ...

Conflicts:
	arch/arm/mach-msm/board-msm7x27.c
	arch/arm/mach-msm/board-msm7x30.c
	arch/arm/mach-msm/board-qsd8x50.c
	arch/arm/mach-msm/board-sapphire.c
	arch/arm/mach-msm/include/mach/memory.h

1 files changed, 145 insertions, 16 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4d266509b451..169db59f6bcb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -7,7 +7,7 @@ config ARM
         select HAVE_MEMBLOCK
         select RTC_LIB
         select SYS_SUPPORTS_APM_EMULATION
-        select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
+        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
         select HAVE_ARCH_KGDB
         select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
@@ -24,7 +24,7 @@ config ARM
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
         select HAVE_REGS_AND_STACK_ACCESS_API
-        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
+        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
         select HAVE_C_RECORDMCOUNT
         select HAVE_GENERIC_HARDIRQS
         select HAVE_SPARSE_IRQ
@@ -63,6 +63,10 @@ config GENERIC_CLOCKEVENTS_BROADCAST
         depends on GENERIC_CLOCKEVENTS
         default y if SMP
 
+config KTIME_SCALAR
+        bool
+        default y
+
 config HAVE_TCM
         bool
         select GENERIC_ALLOCATOR
@@ -178,11 +182,6 @@ config FIQ
 config ARCH_MTD_XIP
         bool
 
-config ARM_L1_CACHE_SHIFT_6
-        bool
-        help
-          Setting ARM L1 cache line size to 64 Bytes.
-
 config VECTORS_BASE
         hex
         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
@@ -191,6 +190,22 @@ config VECTORS_BASE
         help
           The base address of exception vectors.
 
+config ARM_PATCH_PHYS_VIRT
+        bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        depends on !XIP_KERNEL && MMU
+        depends on !ARCH_REALVIEW || !SPARSEMEM
+        help
+          Patch phys-to-virt translation functions at runtime according to
+          the position of the kernel in system memory.
+
+          This can only be used with non-XIP with MMU kernels where
+          the base of physical memory is at a 16MB boundary.
+
+config ARM_PATCH_PHYS_VIRT_16BIT
+        def_bool y
+        depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
@@ -346,7 +361,7 @@ config ARCH_FOOTBRIDGE
         bool "FootBridge"
         select CPU_SA110
         select FOOTBRIDGE
-        select ARCH_USES_GETTIMEOFFSET
+        select GENERIC_CLOCKEVENTS
         help
           Support for systems based on the DC21285 companion chip
           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
@@ -457,6 +472,7 @@ config ARCH_IXP4XX
 
 config ARCH_DOVE
         bool "Marvell Dove"
+        select CPU_V6K
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
@@ -876,6 +892,16 @@ config PLAT_SPEAR
         help
           Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 
+config ARCH_VT8500
+        bool "VIA/WonderMedia 85xx"
+        select CPU_ARM926T
+        select GENERIC_GPIO
+        select ARCH_HAS_CPUFREQ
+        select GENERIC_CLOCKEVENTS
+        select ARCH_REQUIRE_GPIOLIB
+        select HAVE_PWM
+        help
+          Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 endchoice
 
 #
@@ -1008,6 +1034,8 @@ source "arch/arm/mach-versatile/Kconfig"
 
 source "arch/arm/mach-vexpress/Kconfig"
 
+source "arch/arm/mach-vt8500/Kconfig"
+
 source "arch/arm/mach-w90x900/Kconfig"
 
 # Definitions to make life easier
@@ -1049,7 +1077,7 @@ config XSCALE_PMU
         default y
 
 config CPU_HAS_PMU
-        depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
+        depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
                    (!ARCH_OMAP3 || OMAP3_EMU)
         default y
         bool
@@ -1065,7 +1093,7 @@ endif
 
 config ARM_ERRATA_411920
         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
-        depends on CPU_V6
+        depends on CPU_V6 || CPU_V6K
         help
           Invalidation of the Instruction Cache operation can
           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
@@ -1141,7 +1169,7 @@ config ARM_ERRATA_742231
 
 config PL310_ERRATA_588369
         bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
-        depends on CACHE_L2X0 && ARCH_OMAP4
+        depends on CACHE_L2X0
         help
            The PL310 L2 cache controller implements three types of Clean &
            Invalidate maintenance operations: by Physical Address
@@ -1150,8 +1178,7 @@ config PL310_ERRATA_588369
            clean operation followed immediately by an invalidate operation,
            both performing to the same memory location. This functionality
            is not correctly implemented in PL310 as clean lines are not
-           invalidated as a result of these operations. Note that this errata
-           uses Texas Instrument's secure monitor api.
+           invalidated as a result of these operations.
 
 config ARM_ERRATA_720789
         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
@@ -1165,6 +1192,17 @@ config ARM_ERRATA_720789
           tables. The workaround changes the TLB flushing routines to invalidate
           entries regardless of the ASID.
 
+config PL310_ERRATA_727915
+        bool "Background Clean & Invalidate by Way operation can cause data corruption"
+        depends on CACHE_L2X0
+        help
+          PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+          operation (offset 0x7FC). This operation runs in background so that
+          PL310 can handle normal accesses while it is in progress. Under very
+          rare circumstances, due to this erratum, write data can be lost when
+          PL310 treats a cacheable write transaction during a Clean &
+          Invalidate by Way operation.
+
 config ARM_ERRATA_743622
         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
         depends on CPU_V7
@@ -1178,6 +1216,53 @@ config ARM_ERRATA_743622
           visible impact on the overall performance or power consumption of the
           processor.
 
+config ARM_ERRATA_751472
+        bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 751472 Cortex-A9 (prior
+          to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
+          completion of a following broadcasted operation if the second
+          operation is received by a CPU before the ICIALLUIS has completed,
+          potentially leading to corrupted entries in the cache or TLB.
+
+config ARM_ERRATA_753970
+        bool "ARM errata: cache sync operation may be faulty"
+        depends on CACHE_PL310
+        help
+          This option enables the workaround for the 753970 PL310 (r3p0) erratum.
+
+          Under some condition the effect of cache sync operation on
+          the store buffer still remains when the operation completes.
+          This means that the store buffer is always asked to drain and
+          this prevents it from merging any further writes. The workaround
+          is to replace the normal offset of cache sync operation (0x730)
+          by another offset targeting an unmapped PL310 register 0x740.
+          This has the same effect as the cache sync operation: store buffer
+          drain and waiting for all buffers empty.
+
+config ARM_ERRATA_754322
+        bool "ARM errata: possible faulty MMU translations following an ASID switch"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 754322 Cortex-A9 (r2p*,
+          r3p*) erratum. A speculative memory access may cause a page table walk
+          which starts prior to an ASID switch but completes afterwards. This
+          can populate the micro-TLB with a stale entry which may be hit with
+          the new ASID. This workaround places two dsb instructions in the mm
+          switching code so that no page table walks can cross the ASID switch.
+
+config ARM_ERRATA_754327
+        bool "ARM errata: no automatic Store Buffer drain"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 754327 Cortex-A9 (prior to
+          r2p0) erratum. The Store Buffer does not have any automatic draining
+          mechanism and therefore a livelock may occur if an external agent
+          continuously polls a memory location waiting to observe an update.
+          This workaround defines cpu_relax() as smp_mb(), preventing correctly
+          written polling loops from denying visibility of updates to memory.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1251,6 +1336,7 @@ source "kernel/time/Kconfig"
 config SMP
         bool "Symmetric Multi-Processing (EXPERIMENTAL)"
         depends on EXPERIMENTAL
+        depends on CPU_V6K || CPU_V7
         depends on GENERIC_CLOCKEVENTS
         depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
                  MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
@@ -1362,7 +1448,7 @@ config HZ
 
 config THUMB2_KERNEL
         bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
-        depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
+        depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
         select AEABI
         select ARM_ASM_UNIFIED
         help
@@ -1372,6 +1458,37 @@ config THUMB2_KERNEL
 
           If unsure, say N.
 
+config THUMB2_AVOID_R_ARM_THM_JUMP11
+        bool "Work around buggy Thumb-2 short branch relocations in gas"
+        depends on THUMB2_KERNEL && MODULES
+        default y
+        help
+          Various binutils versions can resolve Thumb-2 branches to
+          locally-defined, preemptible global symbols as short-range "b.n"
+          branch instructions.
+
+          This is a problem, because there's no guarantee the final
+          destination of the symbol, or any candidate locations for a
+          trampoline, are within range of the branch.  For this reason, the
+          kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
+          relocation in modules at all, and it makes little sense to add
+          support.
+
+          The symptom is that the kernel fails with an "unsupported
+          relocation" error when loading some modules.
+
+          Until fixed tools are available, passing
+          -fno-optimize-sibling-calls to gcc should prevent gcc generating
+          code which hits this problem, at the cost of a bit of extra runtime
+          stack usage in some cases.
+
+          The problem is described in more detail at:
+              https://bugs.launchpad.net/binutils-linaro/+bug/725126
+
+          Only Thumb-2 kernels are affected.
+
+          Unless you are sure your tools don't have this problem, say Y.
+
 config ARM_ASM_UNIFIED
         bool
 
@@ -1392,7 +1509,7 @@ config AEABI
 
 config OABI_COMPAT
         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
-        depends on AEABI && EXPERIMENTAL
+        depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
         default y
         help
           This option preserves the old syscall interface along with the
@@ -1620,6 +1737,18 @@ config ZBOOT_ROM
           Say Y here if you intend to execute your compressed kernel image
           (zImage) directly from ROM or flash.  If unsure, say N.
 
+config ZBOOT_ROM_MMCIF
+        bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
+        depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
+        help
+          Say Y here to include experimental MMCIF loading code in the
+          ROM-able zImage. With this enabled it is possible to write the
+          the ROM-able zImage kernel image to an MMC card and boot the
+          kernel straight from the reset vector. At reset the processor
+          Mask ROM will load the first part of the the ROM-able zImage
+          which in turn loads the rest the kernel image to RAM using the
+          MMCIF hardware block.
+
 config CMDLINE
         string "Default kernel command string"
         default ""
@@ -1853,7 +1982,7 @@ config FPE_FASTFPE
 
 config VFP
         bool "VFP-format floating point maths"
-        depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
+        depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
         help
           Say Y to include VFP support code in the kernel. This is needed
           if your hardware includes a VFP unit.