[ARM] nommu: manage the CP15 things

All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 2 insertions, 1 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0810d27c039e..2673fee3281c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -621,6 +621,7 @@ config LEDS_CPU
 
 config ALIGNMENT_TRAP
         bool
+        depends on CPU_CP15_MMU
         default y if !ARCH_EBSA110
         help
           ARM processors can not fetch/store information which is not
@@ -852,7 +853,7 @@ source "drivers/base/Kconfig"
 
 source "drivers/connector/Kconfig"
 
-if ALIGNMENT_TRAP
+if ALIGNMENT_TRAP || !CPU_CP15_MMU
 source "drivers/mtd/Kconfig"
 endif