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authorWill Deacon <will.deacon@arm.com>2011-11-14 11:24:57 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-11-21 08:12:18 -0500
commitfa0ce4035d4897b0642132866d896a906429f45e (patch)
tree3c36b35ba449b9745bf44dad4245f1e2b5d4601a /arch/arm/Kconfig
parent11ed0ba1754841316d4095478944300acf19acc3 (diff)
ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds
The Kconfig options for the PL310 errata workarounds do not use a consistent naming scheme for either the config option or the bool description. This patch tidies up the options by ensuring that the bool descriptions are prefixed with "PL310 errata:" and the config options are prefixed with PL310_ERRATA_, making it much clearer in menuconfig as to what the workarounds are for. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r--arch/arm/Kconfig8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 83aa746e71d6..e084b7e981e8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231
1231 capabilities of the processor. 1231 capabilities of the processor.
1232 1232
1233config PL310_ERRATA_588369 1233config PL310_ERRATA_588369
1234 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1234 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1235 depends on CACHE_L2X0 1235 depends on CACHE_L2X0
1236 help 1236 help
1237 The PL310 L2 cache controller implements three types of Clean & 1237 The PL310 L2 cache controller implements three types of Clean &
@@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789
1256 entries regardless of the ASID. 1256 entries regardless of the ASID.
1257 1257
1258config PL310_ERRATA_727915 1258config PL310_ERRATA_727915
1259 bool "Background Clean & Invalidate by Way operation can cause data corruption" 1259 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1260 depends on CACHE_L2X0 1260 depends on CACHE_L2X0
1261 help 1261 help
1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 1262 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
@@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472
1289 operation is received by a CPU before the ICIALLUIS has completed, 1289 operation is received by a CPU before the ICIALLUIS has completed,
1290 potentially leading to corrupted entries in the cache or TLB. 1290 potentially leading to corrupted entries in the cache or TLB.
1291 1291
1292config ARM_ERRATA_753970 1292config PL310_ERRATA_753970
1293 bool "ARM errata: cache sync operation may be faulty" 1293 bool "PL310 errata: cache sync operation may be faulty"
1294 depends on CACHE_PL310 1294 depends on CACHE_PL310
1295 help 1295 help
1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 1296 This option enables the workaround for the 753970 PL310 (r3p0) erratum.