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authorVineet Gupta <vgupta@synopsys.com>2013-09-05 03:33:35 -0400
committerVineet Gupta <vgupta@synopsys.com>2013-11-06 00:11:29 -0500
commitf3e4de327403cee6f76c0dca1b45d6fb0b08daf4 (patch)
tree15ff0625f7848aac0b8d436f497a17a5fd5a4144 /arch/arc
parent064a6269245655b15054ad9783bca9bfd8dc1f9e (diff)
ARC: cacheflush refactor #1: push aux reg ascertaining into leaf routine
ARC dcache supports 3 ops - Inv, Flush, Flush-n-Inv. The programming model however provides 2 commands FLUSH, INV. INV will either discard or flush-n-discard (based on DT_CTRL bit) The leaf helper __dc_line_loop() used to take the AUX register (corresponding to the 2 commands). Now we push that to within the helper, paving way for code consolidations to follow. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/mm/cache_arc700.c16
1 files changed, 6 insertions, 10 deletions
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 5a1259cd948c..2787e5a2c306 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -296,8 +296,10 @@ static inline void __dc_entire_op(const int cacheop)
296 * (aliasing VIPT dcache flushing needs both vaddr and paddr) 296 * (aliasing VIPT dcache flushing needs both vaddr and paddr)
297 */ 297 */
298static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr, 298static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr,
299 unsigned long sz, const int aux_reg) 299 unsigned long sz, const int cacheop)
300{ 300{
301 /* which MMU cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
302 const int aux = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
301 int num_lines; 303 int num_lines;
302 304
303 /* Ensure we properly floor/ceil the non-line aligned/sized requests 305 /* Ensure we properly floor/ceil the non-line aligned/sized requests
@@ -326,11 +328,11 @@ static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr,
326 */ 328 */
327 write_aux_reg(ARC_REG_DC_PTAG, paddr); 329 write_aux_reg(ARC_REG_DC_PTAG, paddr);
328 330
329 write_aux_reg(aux_reg, vaddr); 331 write_aux_reg(aux, vaddr);
330 vaddr += ARC_DCACHE_LINE_LEN; 332 vaddr += ARC_DCACHE_LINE_LEN;
331#else 333#else
332 /* paddr contains stuffed vaddrs bits */ 334 /* paddr contains stuffed vaddrs bits */
333 write_aux_reg(aux_reg, paddr); 335 write_aux_reg(aux, paddr);
334#endif 336#endif
335 paddr += ARC_DCACHE_LINE_LEN; 337 paddr += ARC_DCACHE_LINE_LEN;
336 } 338 }
@@ -346,7 +348,6 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
346 unsigned long sz, const int cacheop) 348 unsigned long sz, const int cacheop)
347{ 349{
348 unsigned long flags, tmp = tmp; 350 unsigned long flags, tmp = tmp;
349 int aux;
350 351
351 local_irq_save(flags); 352 local_irq_save(flags);
352 353
@@ -361,12 +362,7 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
361 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); 362 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
362 } 363 }
363 364
364 if (cacheop & OP_INV) /* Inv / flush-n-inv use same cmd reg */ 365 __dc_line_loop(paddr, vaddr, sz, cacheop);
365 aux = ARC_REG_DC_IVDL;
366 else
367 aux = ARC_REG_DC_FLDL;
368
369 __dc_line_loop(paddr, vaddr, sz, aux);
370 366
371 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */ 367 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
372 wait_for_flush(); 368 wait_for_flush();