ARC: Disintegrate arcregs.h

* Move the various sub-system defines/types into relevant files/functions
  (reduces compilation time)

* move CPU specific stuff out of asm/tlb.h into asm/mmu.h

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

12 files changed, 139 insertions, 162 deletions

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 1b907c465666..20002c46e3bc 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -20,7 +20,6 @@
 #define ARC_REG_PERIBASE_BCR    0x69
 #define ARC_REG_FP_BCR          0x6B    /* Single-Precision FPU */
 #define ARC_REG_DPFP_BCR        0x6C    /* Dbl Precision FPU */
-#define ARC_REG_MMU_BCR         0x6f
 #define ARC_REG_DCCM_BCR        0x74    /* DCCM Present + SZ */
 #define ARC_REG_TIMERS_BCR      0x75
 #define ARC_REG_ICCM_BCR        0x78
@@ -34,22 +33,12 @@
 #define ARC_REG_D_UNCACH_BCR    0x6A
 
 /* status32 Bits Positions */
-#define STATUS_H_BIT            0       /* CPU Halted */
-#define STATUS_E1_BIT           1       /* Int 1 enable */
-#define STATUS_E2_BIT           2       /* Int 2 enable */
-#define STATUS_A1_BIT           3       /* Int 1 active */
-#define STATUS_A2_BIT           4       /* Int 2 active */
 #define STATUS_AE_BIT           5       /* Exception active */
 #define STATUS_DE_BIT           6       /* PC is in delay slot */
 #define STATUS_U_BIT            7       /* User/Kernel mode */
 #define STATUS_L_BIT            12      /* Loop inhibit */
 
 /* These masks correspond to the status word(STATUS_32) bits */
-#define STATUS_H_MASK           (1<<STATUS_H_BIT)
-#define STATUS_E1_MASK          (1<<STATUS_E1_BIT)
-#define STATUS_E2_MASK          (1<<STATUS_E2_BIT)
-#define STATUS_A1_MASK          (1<<STATUS_A1_BIT)
-#define STATUS_A2_MASK          (1<<STATUS_A2_BIT)
 #define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
 #define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
 #define STATUS_U_MASK           (1<<STATUS_U_BIT)
@@ -87,86 +76,7 @@
 /* Auxiliary registers */
 #define AUX_IDENTITY            4
 #define AUX_INTR_VEC_BASE       0x25
-#define AUX_IRQ_LEV             0x200   /* IRQ Priority: L1 or L2 */
-#define AUX_IRQ_HINT            0x201   /* For generating Soft Interrupts */
-#define AUX_IRQ_LV12            0x43    /* interrupt level register */
-
-#define AUX_IENABLE             0x40c
-#define AUX_ITRIGGER            0x40d
-#define AUX_IPULSE              0x415
-
-/* Timer related Aux registers */
-#define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
-#define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
-#define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
-#define ARC_REG_TIMER1_LIMIT    0x102   /* timer 1 limit */
-#define ARC_REG_TIMER1_CTRL     0x101   /* timer 1 control */
-#define ARC_REG_TIMER1_CNT      0x100   /* timer 1 count */
-
-#define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
-#define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
-
-/* MMU Management regs */
-#define ARC_REG_TLBPD0          0x405
-#define ARC_REG_TLBPD1          0x406
-#define ARC_REG_TLBINDEX        0x407
-#define ARC_REG_TLBCOMMAND      0x408
-#define ARC_REG_PID             0x409
-#define ARC_REG_SCRATCH_DATA0   0x418
-
-/* Bits in MMU PID register */
-#define MMU_ENABLE              (1 << 31)       /* Enable MMU for process */
-
-/* Error code if probe fails */
-#define TLB_LKUP_ERR            0x80000000
-
-/* TLB Commands */
-#define TLBWrite    0x1
-#define TLBRead     0x2
-#define TLBGetIndex 0x3
-#define TLBProbe    0x4
-
-#if (CONFIG_ARC_MMU_VER >= 2)
-#define TLBWriteNI  0x5         /* write JTLB without inv uTLBs */
-#define TLBIVUTLB   0x6         /* explicitly inv uTLBs */
-#else
-#undef TLBWriteNI               /* These cmds don't exist on older MMU */
-#undef TLBIVUTLB
-#endif
-
-/* Instruction cache related Auxiliary registers */
-#define ARC_REG_IC_BCR          0x77    /* Build Config reg */
-#define ARC_REG_IC_IVIC         0x10
-#define ARC_REG_IC_CTRL         0x11
-#define ARC_REG_IC_IVIL         0x19
-#if (CONFIG_ARC_MMU_VER > 2)
-#define ARC_REG_IC_PTAG         0x1E
-#endif
-
-/* Bit val in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE   0x1
-
-/* Data cache related Auxiliary registers */
-#define ARC_REG_DC_BCR          0x72
-#define ARC_REG_DC_IVDC         0x47
-#define ARC_REG_DC_CTRL         0x48
-#define ARC_REG_DC_IVDL         0x4A
-#define ARC_REG_DC_FLSH         0x4B
-#define ARC_REG_DC_FLDL         0x4C
-#if (CONFIG_ARC_MMU_VER > 2)
-#define ARC_REG_DC_PTAG         0x5C
-#endif
 
-/* Bit val in DC_CTRL */
-#define DC_CTRL_INV_MODE_FLUSH  0x40
-#define DC_CTRL_FLUSH_STATUS    0x100
-
-/* MMU Management regs */
-#define ARC_REG_PID             0x409
-#define ARC_REG_SCRATCH_DATA0   0x418
-
-/* Bits in MMU PID register */
-#define MMU_ENABLE              (1 << 31)       /* Enable MMU for process */
 
 /*
  * Floating Pt Registers
@@ -293,24 +203,6 @@ struct bcr_identity {
 #endif
 };
 
-struct bcr_mmu_1_2 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-        unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
-#else
-        unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
-#endif
-};
-
-struct bcr_mmu_3 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-        unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
-                     u_itlb:4, u_dtlb:4;
-#else
-        unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
-                     ways:4, ver:8;
-#endif
-};
-
 #define EXTN_SWAP_VALID     0x1
 #define EXTN_NORM_VALID     0x2
 #define EXTN_MINMAX_VALID   0x2
@@ -343,14 +235,6 @@ struct bcr_extn_xymem {
 #endif
 };
 
-struct bcr_cache {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-        unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
-#else
-        unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
-#endif
-};
-
 struct bcr_perip {
 #ifdef CONFIG_CPU_BIG_ENDIAN
         unsigned int start:8, pad2:8, sz:8, pad:8;
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 2fe8e41a551c..44eb07eb92e5 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -9,8 +9,6 @@
 #ifndef __ARC_ASM_CACHE_H
 #define __ARC_ASM_CACHE_H
 
-#include <asm/mmu.h>    /* some of cache registers depend on MMU ver */
-
 /* In case $$ not config, setup a dummy number for rest of kernel */
 #ifndef CONFIG_ARC_CACHE_LINE_SHIFT
 #define L1_CACHE_SHIFT          6
@@ -36,6 +34,13 @@
 #define is_not_cache_aligned(p) ((unsigned long)p & (~DCACHE_LINE_MASK))
 #endif
 
+/*
+ * ARC700 doesn't cache any access in top 256M.
+ * Ideal for wiring memory mapped peripherals as we don't need to do
+ * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
+ */
+#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
+
 #ifndef __ASSEMBLY__
 
 /* Uncached access macros */
@@ -59,16 +64,10 @@
 
 #define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
 
-/*
- * ARC700 doesn't cache any access in top 256M.
- * Ideal for wiring memory mapped peripherals as we don't need to do
- * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
- */
-#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
-
 extern void arc_cache_init(void);
 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
 extern void __init read_decode_cache_bcr(void);
-#endif
+
+#endif  /* !__ASSEMBLY__ */
 
 #endif /* _ASM_CACHE_H */
diff --git a/arch/arc/include/asm/irqflags.h b/arch/arc/include/asm/irqflags.h
index eac071668201..d99f79bcf865 100644
--- a/arch/arc/include/asm/irqflags.h
+++ b/arch/arc/include/asm/irqflags.h
@@ -19,6 +19,26 @@
 
 #include <asm/arcregs.h>
 
+/* status32 Reg bits related to Interrupt Handling */
+#define STATUS_E1_BIT           1       /* Int 1 enable */
+#define STATUS_E2_BIT           2       /* Int 2 enable */
+#define STATUS_A1_BIT           3       /* Int 1 active */
+#define STATUS_A2_BIT           4       /* Int 2 active */
+
+#define STATUS_E1_MASK          (1<<STATUS_E1_BIT)
+#define STATUS_E2_MASK          (1<<STATUS_E2_BIT)
+#define STATUS_A1_MASK          (1<<STATUS_A1_BIT)
+#define STATUS_A2_MASK          (1<<STATUS_A2_BIT)
+
+/* Other Interrupt Handling related Aux regs */
+#define AUX_IRQ_LEV             0x200   /* IRQ Priority: L1 or L2 */
+#define AUX_IRQ_HINT            0x201   /* For generating Soft Interrupts */
+#define AUX_IRQ_LV12            0x43    /* interrupt level register */
+
+#define AUX_IENABLE             0x40c
+#define AUX_ITRIGGER            0x40d
+#define AUX_IPULSE              0x415
+
 #ifndef __ASSEMBLY__
 
 /******************************************************************
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 33548f975cd2..7c03fe61759c 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -17,6 +17,32 @@
 #define CONFIG_ARC_MMU_VER 3
 #endif
 
+/* MMU Management regs */
+#define ARC_REG_MMU_BCR         0x06f
+#define ARC_REG_TLBPD0          0x405
+#define ARC_REG_TLBPD1          0x406
+#define ARC_REG_TLBINDEX        0x407
+#define ARC_REG_TLBCOMMAND      0x408
+#define ARC_REG_PID             0x409
+#define ARC_REG_SCRATCH_DATA0   0x418
+
+/* Bits in MMU PID register */
+#define MMU_ENABLE              (1 << 31)       /* Enable MMU for process */
+
+/* Error code if probe fails */
+#define TLB_LKUP_ERR            0x80000000
+
+/* TLB Commands */
+#define TLBWrite    0x1
+#define TLBRead     0x2
+#define TLBGetIndex 0x3
+#define TLBProbe    0x4
+
+#if (CONFIG_ARC_MMU_VER >= 2)
+#define TLBWriteNI  0x5         /* write JTLB without inv uTLBs */
+#define TLBIVUTLB   0x6         /* explicitly inv uTLBs */
+#endif
+
 #ifndef __ASSEMBLY__
 
 typedef struct {
@@ -26,6 +52,16 @@ typedef struct {
 #endif
 } mm_context_t;
 
+#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
+void tlb_paranoid_check(unsigned int pid_sw, unsigned long address);
+#else
+#define tlb_paranoid_check(a, b)
 #endif
 
+void arc_mmu_init(void);
+extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
+void __init read_decode_mmu_bcr(void);
+
+#endif  /* !__ASSEMBLY__ */
+
 #endif
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 95b1522212a7..f31dc817fe12 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -135,6 +135,12 @@
 /* ioremap */
 #define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
 
+/* Masks for actual TLB "PD"s */
+#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
+#define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \
+                         _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
+                         _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
+
 /**************************************************************************
  * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
  *
diff --git a/arch/arc/include/asm/tlb-mmu1.h b/arch/arc/include/asm/tlb-mmu1.h
index 351ae6568d0a..8a1ec96012ae 100644
--- a/arch/arc/include/asm/tlb-mmu1.h
+++ b/arch/arc/include/asm/tlb-mmu1.h
@@ -10,7 +10,6 @@
 #define __ASM_TLB_MMU_V1_H__
 
 #include <asm/mmu.h>
-#include <asm/tlb.h>
 
 #if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)
 
diff --git a/arch/arc/include/asm/tlb.h b/arch/arc/include/asm/tlb.h
index cb0c708ca665..a9db5f62aaf3 100644
--- a/arch/arc/include/asm/tlb.h
+++ b/arch/arc/include/asm/tlb.h
@@ -9,18 +9,6 @@
 #ifndef _ASM_ARC_TLB_H
 #define _ASM_ARC_TLB_H
 
-#ifdef __KERNEL__
-
-#include <asm/pgtable.h>
-
-/* Masks for actual TLB "PD"s */
-#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
-#define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \
-                         _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
-                         _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
-
-#ifndef __ASSEMBLY__
-
 #define tlb_flush(tlb)                          \
 do {                                            \
         if (tlb->fullmm)                        \
@@ -56,18 +44,4 @@ do {									\
 #include <linux/pagemap.h>
 #include <asm-generic/tlb.h>
 
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-void tlb_paranoid_check(unsigned int pid_sw, unsigned long address);
-#else
-#define tlb_paranoid_check(a, b)
-#endif
-
-void arc_mmu_init(void);
-extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
-void __init read_decode_mmu_bcr(void);
-
-#endif  /* __ASSEMBLY__ */
-
-#endif  /* __KERNEL__ */
-
 #endif /* _ASM_ARC_TLB_H */
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 09f4309aa2c0..32afa54a585d 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -44,6 +44,17 @@
 #include <asm/clk.h>
 #include <asm/mach_desc.h>
 
+/* Timer related Aux registers */
+#define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
+#define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
+#define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
+#define ARC_REG_TIMER1_LIMIT    0x102   /* timer 1 limit */
+#define ARC_REG_TIMER1_CTRL     0x101   /* timer 1 control */
+#define ARC_REG_TIMER1_CNT      0x100   /* timer 1 count */
+
+#define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
+#define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
+
 #define ARC_TIMER_MAX   0xFFFFFFFF
 
 /********** Clock Source Device *********/
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 28007d25066e..e9c7a66817ca 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -73,6 +73,33 @@
 #include <asm/cachectl.h>
 #include <asm/setup.h>
 
+/* Instruction cache related Auxiliary registers */
+#define ARC_REG_IC_BCR          0x77    /* Build Config reg */
+#define ARC_REG_IC_IVIC         0x10
+#define ARC_REG_IC_CTRL         0x11
+#define ARC_REG_IC_IVIL         0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_REG_IC_PTAG         0x1E
+#endif
+
+/* Bit val in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE   0x1
+
+/* Data cache related Auxiliary registers */
+#define ARC_REG_DC_BCR          0x72    /* Build Config reg */
+#define ARC_REG_DC_IVDC         0x47
+#define ARC_REG_DC_CTRL         0x48
+#define ARC_REG_DC_IVDL         0x4A
+#define ARC_REG_DC_FLSH         0x4B
+#define ARC_REG_DC_FLDL         0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_REG_DC_PTAG         0x5C
+#endif
+
+/* Bit val in DC_CTRL */
+#define DC_CTRL_INV_MODE_FLUSH  0x40
+#define DC_CTRL_FLUSH_STATUS    0x100
+
 char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
 {
         int n = 0;
@@ -104,9 +131,15 @@ char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
  */
 void __cpuinit read_decode_cache_bcr(void)
 {
-        struct bcr_cache ibcr, dbcr;
         struct cpuinfo_arc_cache *p_ic, *p_dc;
         unsigned int cpu = smp_processor_id();
+        struct bcr_cache {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+                unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
+#else
+                unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
+#endif
+        } ibcr, dbcr;
 
         p_ic = &cpuinfo_arc700[cpu].icache;
         READ_BCR(ARC_REG_IC_BCR, ibcr);
@@ -136,12 +169,10 @@ void __cpuinit read_decode_cache_bcr(void)
  */
 void __cpuinit arc_cache_init(void)
 {
-        unsigned int temp;
         unsigned int cpu = smp_processor_id();
         struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
         struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
-        int way_pg_ratio = way_pg_ratio;
-        int dcache_does_alias;
+        unsigned int dcache_does_alias, temp;
         char str[256];
 
         printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 689ffd86d5e9..c0decc1f8d22 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -15,6 +15,7 @@
 #include <linux/uaccess.h>
 #include <linux/kdebug.h>
 #include <asm/pgalloc.h>
+#include <asm/mmu.h>
 
 static int handle_vmalloc_fault(struct mm_struct *mm, unsigned long address)
 {
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 1ced5f18e6b3..f60807c2683d 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -55,7 +55,7 @@
 #include <asm/arcregs.h>
 #include <asm/setup.h>
 #include <asm/mmu_context.h>
-#include <asm/tlb.h>
+#include <asm/mmu.h>
 
 /*                      Need for ARC MMU v2
  *
@@ -97,6 +97,7 @@
  * J-TLB entry got evicted/replaced.
  */
 
+
 /* A copy of the ASID from the PID reg is kept in asid_cache */
 int asid_cache = FIRST_ASID;
 
@@ -466,10 +467,25 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
  */
 void __cpuinit read_decode_mmu_bcr(void)
 {
-        unsigned int tmp;
-        struct bcr_mmu_1_2 *mmu2;       /* encoded MMU2 attr */
-        struct bcr_mmu_3 *mmu3;         /* encoded MMU3 attr */
         struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
+        unsigned int tmp;
+        struct bcr_mmu_1_2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+                unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
+#else
+                unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
+#endif
+        } *mmu2;
+
+        struct bcr_mmu_3 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
+                     u_itlb:4, u_dtlb:4;
+#else
+        unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
+                     ways:4, ver:8;
+#endif
+        } *mmu3;
 
         tmp = read_aux_reg(ARC_REG_MMU_BCR);
         mmu->ver = (tmp >> 24);
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 3357d26ffe54..7bf811d51af8 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -39,7 +39,7 @@
 
 #include <linux/linkage.h>
 #include <asm/entry.h>
-#include <asm/tlb.h>
+#include <asm/mmu.h>
 #include <asm/pgtable.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>