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authorMasanari Iida <standby24x7@gmail.com>2013-03-16 07:53:05 -0400
committerJiri Kosina <jkosina@suse.cz>2013-03-18 09:57:53 -0400
commitcf2fbdd26f80046725a11a80683a03baf27fae82 (patch)
tree159d41ee54caf37e52835c072b835df57a0a235f /arch/arc/plat-arcfpga
parentce03cb20640b94d6124decec36db4d84ee30c83c (diff)
treewide: Fix typos in printk and comment
Signed-off-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch/arc/plat-arcfpga')
-rw-r--r--arch/arc/plat-arcfpga/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig
index b41e786cdbc0..295cefeb25d3 100644
--- a/arch/arc/plat-arcfpga/Kconfig
+++ b/arch/arc/plat-arcfpga/Kconfig
@@ -53,7 +53,7 @@ menuconfig ARC_HAS_BVCI_LAT_UNIT
53 bool "BVCI Bus Latency Unit" 53 bool "BVCI Bus Latency Unit"
54 depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4 54 depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
55 help 55 help
56 IP to add artifical latency to BVCI Bus Based FPGA builds. 56 IP to add artificial latency to BVCI Bus Based FPGA builds.
57 The default latency (even worst case) for FPGA is non-realistic 57 The default latency (even worst case) for FPGA is non-realistic
58 (~10 SDRAM, ~5 SSRAM). 58 (~10 SDRAM, ~5 SSRAM).
59 59