ARC: Disable caches in early boot if so configured

Requested-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

1 files changed, 35 insertions, 3 deletions

diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 4ad04915dc6b..07a58f2d3077 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -12,10 +12,42 @@
  *      to skip certain things during boot on simulator
  */
 
+#include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/entry.h>
-#include <linux/linkage.h>
 #include <asm/arcregs.h>
+#include <asm/cache.h>
+
+.macro CPU_EARLY_SETUP
+
+        ; Setting up Vectror Table (in case exception happens in early boot
+        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
+
+        ; Disable I-cache/D-cache if kernel so configured
+        lr      r5, [ARC_REG_IC_BCR]
+        breq    r5, 0, 1f               ; I$ doesn't exist
+        lr      r5, [ARC_REG_IC_CTRL]
+#ifdef CONFIG_ARC_HAS_ICACHE
+        bclr    r5, r5, 0               ; 0 - Enable, 1 is Disable
+#else
+        bset    r5, r5, 0               ; I$ exists, but is not used
+#endif
+        sr      r5, [ARC_REG_IC_CTRL]
+
+1:
+        lr      r5, [ARC_REG_DC_BCR]
+        breq    r5, 0, 1f               ; D$ doesn't exist
+        lr      r5, [ARC_REG_DC_CTRL]
+        bclr    r5, r5, 6               ; Invalidate (discard w/o wback)
+#ifdef CONFIG_ARC_HAS_DCACHE
+        bclr    r5, r5, 0               ; Enable (+Inv)
+#else
+        bset    r5, r5, 0               ; Disable (+Inv)
+#endif
+        sr      r5, [ARC_REG_DC_CTRL]
+
+1:
+.endm
 
         .cpu A7
 
@@ -27,7 +59,7 @@ stext:
         ; Don't clobber r0-r2 yet. It might have bootloader provided info
         ;-------------------------------------------------------------------
 
-        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
+        CPU_EARLY_SETUP
 
 #ifdef CONFIG_SMP
         ; Ensure Boot (Master) proceeds. Others wait in platform dependent way
@@ -90,7 +122,7 @@ stext:
 
 first_lines_of_secondary:
 
-        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
+        CPU_EARLY_SETUP
 
         ; setup per-cpu idle task as "current" on this CPU
         ld      r0, [@secondary_idle_tsk]