Merge branch 'pci/resource' into next

* pci/resource:
  PCI: Allocate 64-bit BARs above 4G when possible
  PCI: Enforce bus address limits in resource allocation
  PCI: Split out bridge window override of minimum allocation address
  agp/ati: Use PCI_COMMAND instead of hard-coded 4
  agp/intel: Use CPU physical address, not bus address, for ioremap()
  agp/intel: Use pci_bus_address() to get GTTADR bus address
  agp/intel: Use pci_bus_address() to get MMADR bus address
  agp/intel: Support 64-bit GMADR
  agp/intel: Rename gtt_bus_addr to gtt_phys_addr
  drm/i915: Rename gtt_bus_addr to gtt_phys_addr
  agp: Use pci_resource_start() to get CPU physical address for BAR
  agp: Support 64-bit APBASE
  PCI: Add pci_bus_address() to get bus address of a BAR
  PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
  PCI: Change pci_bus_region addresses to dma_addr_t

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/alpha/kernel/pci-sysfs.c b/arch/alpha/kernel/pci-sysfs.c
index 2b183b0d3207..99e8d4796c96 100644
--- a/arch/alpha/kernel/pci-sysfs.c
+++ b/arch/alpha/kernel/pci-sysfs.c
@@ -83,7 +83,7 @@ static int pci_mmap_resource(struct kobject *kobj,
         if (iomem_is_exclusive(res->start))
                 return -EINVAL;
 
-        pcibios_resource_to_bus(pdev, &bar, res);
+        pcibios_resource_to_bus(pdev->bus, &bar, res);
         vma->vm_pgoff += bar.start >> (PAGE_SHIFT - (sparse ? 5 : 0));
         mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
 
@@ -139,7 +139,7 @@ static int sparse_mem_mmap_fits(struct pci_dev *pdev, int num)
         long dense_offset;
         unsigned long sparse_size;
 
-        pcibios_resource_to_bus(pdev, &bar, &pdev->resource[num]);
+        pcibios_resource_to_bus(pdev->bus, &bar, &pdev->resource[num]);
 
         /* All core logic chips have 4G sparse address space, except
            CIA which has 16G (see xxx_SPARSE_MEM and xxx_DENSE_MEM