Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

1 files changed, 49 insertions, 0 deletions

diff --git a/arch/alpha/kernel/es1888.c b/arch/alpha/kernel/es1888.c
new file mode 100644
index 000000000000..d584c85fea7a
--- /dev/null
+++ b/arch/alpha/kernel/es1888.c
@@ -0,0 +1,49 @@
+/*
+ *      linux/arch/alpha/kernel/es1888.c
+ *
+ * Init the built-in ES1888 sound chip (SB16 compatible)
+ */
+
+#include <linux/init.h>
+#include <asm/io.h>
+#include "proto.h"
+
+void __init
+es1888_init(void)
+{
+        /* Sequence of IO reads to init the audio controller */
+        inb(0x0229);
+        inb(0x0229);
+        inb(0x0229);
+        inb(0x022b);
+        inb(0x0229);
+        inb(0x022b);
+        inb(0x0229);
+        inb(0x0229);
+        inb(0x022b);
+        inb(0x0229);
+        inb(0x0220); /* This sets the base address to 0x220 */
+
+        /* Sequence to set DMA channels */
+        outb(0x01, 0x0226);             /* reset */
+        inb(0x0226);                    /* pause */
+        outb(0x00, 0x0226);             /* release reset */
+        while (!(inb(0x022e) & 0x80))   /* wait for bit 7 to assert*/
+                continue;
+        inb(0x022a);                    /* pause */
+        outb(0xc6, 0x022c);             /* enable extended mode */
+        inb(0x022a);                    /* pause, also forces the write */
+        while (inb(0x022c) & 0x80)      /* wait for bit 7 to deassert */
+                continue;
+        outb(0xb1, 0x022c);             /* setup for write to Interrupt CR */
+        while (inb(0x022c) & 0x80)      /* wait for bit 7 to deassert */
+                continue;
+        outb(0x14, 0x022c);             /* set IRQ 5 */
+        while (inb(0x022c) & 0x80)      /* wait for bit 7 to deassert */
+                continue;
+        outb(0xb2, 0x022c);             /* setup for write to DMA CR */
+        while (inb(0x022c) & 0x80)      /* wait for bit 7 to deassert */
+                continue;
+        outb(0x18, 0x022c);             /* set DMA channel 1 */
+        inb(0x022c);                    /* force the write */
+}