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authorH. Peter Anvin <hpa@zytor.com>2008-09-04 12:04:45 -0400
committerH. Peter Anvin <hpa@zytor.com>2008-09-04 12:04:45 -0400
commitfe47784ba5cbb6b713c013e046859946789b45e4 (patch)
tree6384958d55e29be0d2eb8ae78fa437c10636d8d6 /arch/alpha/include/asm/cache.h
parent83b8e28b14d63db928cb39e5c5ed2a548246bd71 (diff)
parentaf2e1f276ff08f17192411ea3b71c13a758dfe12 (diff)
Merge branch 'x86/cpu' into x86/xsave
Conflicts: arch/x86/kernel/cpu/feature_names.c include/asm-x86/cpufeature.h
Diffstat (limited to 'arch/alpha/include/asm/cache.h')
-rw-r--r--arch/alpha/include/asm/cache.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/alpha/include/asm/cache.h b/arch/alpha/include/asm/cache.h
new file mode 100644
index 000000000000..f199e69a5d0b
--- /dev/null
+++ b/arch/alpha/include/asm/cache.h
@@ -0,0 +1,23 @@
1/*
2 * include/asm-alpha/cache.h
3 */
4#ifndef __ARCH_ALPHA_CACHE_H
5#define __ARCH_ALPHA_CACHE_H
6
7
8/* Bytes per L1 (data) cache line. */
9#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6)
10# define L1_CACHE_BYTES 64
11# define L1_CACHE_SHIFT 6
12#else
13/* Both EV4 and EV5 are write-through, read-allocate,
14 direct-mapped, physical.
15*/
16# define L1_CACHE_BYTES 32
17# define L1_CACHE_SHIFT 5
18#endif
19
20#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
21#define SMP_CACHE_BYTES L1_CACHE_BYTES
22
23#endif