diff options
| author | Axel Lin <axel.lin@gmail.com> | 2011-10-23 23:32:41 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2011-10-24 08:09:42 -0400 |
| commit | 49fa4d9b5aeafb985abe8cb8cdf6432690c49ad3 (patch) | |
| tree | 4c3aee893aa2818d83a1ff5f9691b5749b9cb1b9 /Makefile | |
| parent | 753ddf52153b60be924109df3bebab0cd60b3297 (diff) | |
ASoC: wm8940: Fix setting PLL Output clock division ratio
According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of
WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions