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authorDimitri Sivanich <sivanich@sgi.com>2011-05-06 11:33:44 -0400
committerDan Williams <dan.j.williams@intel.com>2011-05-26 20:11:24 -0400
commit19d78a61be6dd707dcec298c486303d4ba2c840a (patch)
tree57c0bc50540ec0f49b7b972f14cee51bc4f22e60 /MAINTAINERS
parent5dbd05d46fb7d849570c8fa09d48591aa7ce1766 (diff)
x86: poll waiting for I/OAT DMA channel status
For certain system configurations a 5 usec udelay before checking I/OAT DMA channel status is sometimes not sufficient, resulting in a false failure status and unnecessary freeing of channel resources. Conversely, for many configurations 5 usec is longer than necessary. Loop for up to 20 usec waiting for successful status before failing. Signed-off-by: Dimitri Sivanich <sivanich@sgi.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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