CLK: TI: add support for gate clock

This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 85 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt
new file mode 100644
index 000000000000..125281aaa4ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/gate.txt
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+Binding for Texas Instruments gate clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however,
+it supports a number of additional features. If no register
+is provided for this clock, the code assumes that a clockdomain
+will be controlled instead and the corresponding hw-ops for
+that is used.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/gate-clock.txt
+[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+Required properties:
+- compatible : shall be one of:
+  "ti,gate-clock" - basic gate clock
+  "ti,wait-gate-clock" - gate clock which waits until clock is active before
+                         returning from clk_enable()
+  "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
+  "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
+  "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
+                          clock directly from a clockdomain, see [3] how
+                          to map clockdomains properly
+  "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
+                          required for a hardware errata
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock
+- reg : offset for register controlling adjustable gate, not needed for
+        ti,clkdm-gate-clock type
+
+Optional properties:
+- ti,bit-shift : bit shift for programming the clock gate, invalid for
+                 ti,clkdm-gate-clock type
+- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
+  gates the clock and clearing the bit ungates the clock.
+
+Examples:
+        mmchs2_fck: mmchs2_fck@48004a00 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x48004a00 0x4>;
+                ti,bit-shift = <25>;
+        };
+
+        uart4_fck_am35xx: uart4_fck_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <23>;
+        };
+
+        dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
+                #clock-cells = <0>;
+                compatible = "ti,dss-gate-clock";
+                clocks = <&dpll4_m4x2_ck>;
+                reg = <0x48004e00 0x4>;
+                ti,bit-shift = <0>;
+        };
+
+        emac_ick: emac_ick@4800259c {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x4800259c 0x4>;
+                ti,bit-shift = <1>;
+        };
+
+        emu_src_ck: emu_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,clkdm-gate-clock";
+                clocks = <&emu_src_mux_ck>;
+        };
+
+        dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m2x2_mul_ck>;
+                ti,bit-shift = <0x1b>;
+                reg = <0x48004d00 0x4>;
+                ti,set-bit-to-disable;
+        };