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authorLinus Torvalds <torvalds@linux-foundation.org>2012-10-07 07:55:16 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-10-07 07:55:16 -0400
commit5e090ed7af10729a396a25df43d69a236e789736 (patch)
tree09ba2dd9974b5224721fbc413bcf6ac9b2ac73f9 /Documentation
parent84424026c0a910886064049d414a12a4f4dd125e (diff)
parent54d69df5849ec2e660aa12ac75562618c10fb499 (diff)
Merge tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull late ARM soc platform updates from Olof Johansson: "This branch contains updates to OMAP and Marvell platforms (kirkwood, dove, mvebu) that came in after we had done the big multiplatform merges, so they were kept separate from the rest, and not separated into the traditional topics of cleanup/driver/platform features. For OMAP, the updates are: - Runtime PM conversions for the GPMC and RNG IP blocks - Preparation patches for the OMAP common clock framework conversion - clkdev alias additions required by other drivers - Performance Monitoring Unit (PMU) support for OMAP2, 3, and non-4430 OMAP4 - OMAP hwmod code and data improvements - Preparation patches for the IOMMU runtime PM conversion - Preparation patches for OMAP4 full-chip retention support For Kirkwood/Dove/mvebu: - New driver for "address decoder controller" for mvebu, which is a piece of hardware that configures addressable devices and peripherals. First user is the boot rom aperture on armada XP since it is needed for SMP support. - New device tree bindings for peripherals such as gpio-fan, iconnect nand, mv_cesa and the above address decoder controller. - Some defconfig updates, mostly to enable new DT boards and a few drivers. - New drivers using the pincontrol subsystem for dove, kirkwood and mvebu - New clean gpio driver for mvebu" * tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits) ARM: mvebu: fix build breaks from multi-platform conversion ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70 ARM: OMAP2+: PMU: Add runtime PM support ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD ARM: OMAP3: hwmod data: Add debugss HWMOD data ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP hwrng: OMAP: remove SoC restrictions from driver registration ARM: OMAP: split OMAP1, OMAP2+ RNG device registration hwrng: OMAP: convert to use runtime PM hwrng: OMAP: store per-device data in per-device variables, not file statics ARM: OMAP2xxx: hwmod/CM: add RNG integration data ARM: OMAP2+: gpmc: minimal driver support ARM: OMAP2+: gpmc: Adapt to HWMOD ARM: OMAP2/3: hwmod data: add gpmc ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp ARM: OMAP3: hwmod data: add mmu data for iva and isp ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/crypto/mv_cesa.txt20
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-fan.txt25
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-mvebu.txt53
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt95
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt100
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt72
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt279
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt46
8 files changed, 690 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
new file mode 100644
index 000000000000..47229b1a594b
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
@@ -0,0 +1,20 @@
1Marvell Cryptographic Engines And Security Accelerator
2
3Required properties:
4- compatible : should be "marvell,orion-crypto"
5- reg : base physical address of the engine and length of memory mapped
6 region, followed by base physical address of sram and its memory
7 length
8- reg-names : "regs" , "sram";
9- interrupts : interrupt number
10
11Examples:
12
13 crypto@30000 {
14 compatible = "marvell,orion-crypto";
15 reg = <0x30000 0x10000>,
16 <0x4000000 0x800>;
17 reg-names = "regs" , "sram";
18 interrupts = <22>;
19 status = "okay";
20 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-fan.txt b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
new file mode 100644
index 000000000000..2dd457a3469a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
@@ -0,0 +1,25 @@
1Bindings for fan connected to GPIO lines
2
3Required properties:
4- compatible : "gpio-fan"
5- gpios: Specifies the pins that map to bits in the control value,
6 ordered MSB-->LSB.
7- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
8 control value that should be set to achieve them. This array
9 must have the RPM values in ascending order.
10
11Optional properties:
12- alarm-gpios: This pin going active indicates something is wrong with
13 the fan, and a udev event will be fired.
14
15Examples:
16
17 gpio_fan {
18 compatible = "gpio-fan";
19 gpios = <&gpio1 14 1
20 &gpio1 13 1>;
21 gpio-fan,speed-map = <0 0
22 3000 1
23 6000 2>;
24 alarm-gpios = <&gpio1 15 1>;
25 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
new file mode 100644
index 000000000000..a6f3bec1da7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -0,0 +1,53 @@
1* Marvell EBU GPIO controller
2
3Required properties:
4
5- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
6 or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
7 Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
8 370. "marvell,mv78200-gpio" should be used for the Discovery
9 MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
10 SoCs (MV78230, MV78260, MV78460).
11
12- reg: Address and length of the register set for the device. Only one
13 entry is expected, except for the "marvell,armadaxp-gpio" variant
14 for which two entries are expected: one for the general registers,
15 one for the per-cpu registers.
16
17- interrupts: The list of interrupts that are used for all the pins
18 managed by this GPIO bank. There can be more than one interrupt
19 (example: 1 interrupt per 8 pins on Armada XP, which means 4
20 interrupts per bank of 32 GPIOs).
21
22- interrupt-controller: identifies the node as an interrupt controller
23
24- #interrupt-cells: specifies the number of cells needed to encode an
25 interrupt source. Should be two.
26 The first cell is the GPIO number.
27 The second cell is used to specify flags:
28 bits[3:0] trigger type and level flags:
29 1 = low-to-high edge triggered.
30 2 = high-to-low edge triggered.
31 4 = active high level-sensitive.
32 8 = active low level-sensitive.
33
34- gpio-controller: marks the device node as a gpio controller
35
36- ngpios: number of GPIOs this controller has
37
38- #gpio-cells: Should be two. The first cell is the pin number. The
39 second cell is reserved for flags, unused at the moment.
40
41Example:
42
43 gpio0: gpio@d0018100 {
44 compatible = "marvell,armadaxp-gpio";
45 reg = <0xd0018100 0x40>,
46 <0xd0018800 0x30>;
47 ngpios = <32>;
48 gpio-controller;
49 #gpio-cells = <2>;
50 interrupt-controller;
51 #interrupt-cells = <2>;
52 interrupts = <16>, <17>, <18>, <19>;
53 };
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
new file mode 100644
index 000000000000..01ef408e205f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -0,0 +1,95 @@
1* Marvell Armada 370 SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6710-pinctrl"
8
9Available mpp pins/groups and functions:
10Note: brackets (x) are not part of the mpp name for marvell,function and given
11only for more detailed description in this document.
12
13name pins functions
14================================================================================
15mpp0 0 gpio, uart0(rxd)
16mpp1 1 gpo, uart0(txd)
17mpp2 2 gpio, i2c0(sck), uart0(txd)
18mpp3 3 gpio, i2c0(sda), uart0(rxd)
19mpp4 4 gpio, cpu_pd(vdd)
20mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
21mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
22mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
23mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
24mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
25mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
26mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
27 sata1(prsnt), spi1(cs1)
28mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
29 audio(spdifi)
30mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
31 audio(rmclk)
32mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
33 spi0(cs2)
34mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
35 spi0(cs3)
36mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
37mpp17 17 gpo, ge(mdc)
38mpp18 18 gpio, ge(mdio)
39mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
40mpp20 20 gpo, ge0(txd4), ge1(txd0)
41mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
42mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
43mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
44mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
45mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
46mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
47mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
48mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
49mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
50mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
51mpp31 31 gpio, tclk, ge0(txerr)
52mpp32 32 gpio, spi0(cs0)
53mpp33 33 gpio, dev(bootcs), spi0(cs0)
54mpp34 34 gpo, dev(wen0), spi0(mosi)
55mpp35 35 gpo, dev(oen), spi0(sck)
56mpp36 36 gpo, dev(a1), spi0(miso)
57mpp37 37 gpo, dev(a0), sata0(prsnt)
58mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
59mpp39 39 gpo, dev(ad0), audio(spdifo)
60mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
61mpp41 41 gpio, dev(ad2), uart1(rxd)
62mpp42 42 gpo, dev(ad3), uart1(txd)
63mpp43 43 gpo, dev(ad4), audio(bclk)
64mpp44 44 gpo, dev(ad5), audio(mclk)
65mpp45 45 gpo, dev(ad6), audio(lrclk)
66mpp46 46 gpo, dev(ad7), audio(sdo)
67mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
68mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
69 spi0(cs1)
70mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
71 audio(spdifi)
72mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
73 audio(rmclk)
74mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
75mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
76mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
77 pcie(clkreq1)
78mpp54 54 gpo, dev(ad15), tdm(dtx)
79mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
80 sata0(prsnt)
81mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
82 pcie(clkreq0), spi1(cs1)
83mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
84 audio(sdo)
85mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
86 uart0(rts)
87mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
88mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
89 audio(sdi)
90mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
91mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
92 audio(mclk), uart0(cts)
93mpp63 63 gpo, spi0(sck), tclk
94mpp64 64 gpio, spi0(miso), spi0-1(cs1)
95mpp65 65 gpio, spi0(mosi), spi0-1(cs2)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
new file mode 100644
index 000000000000..bfa0a2e5e0cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -0,0 +1,100 @@
1* Marvell Armada XP SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9
10This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
11
12Available mpp pins/groups and functions:
13Note: brackets (x) are not part of the mpp name for marvell,function and given
14only for more detailed description in this document.
15
16* Marvell Armada XP (all variants)
17
18name pins functions
19================================================================================
20mpp0 0 gpio, ge0(txclko), lcd(d0)
21mpp1 1 gpio, ge0(txd0), lcd(d1)
22mpp2 2 gpio, ge0(txd1), lcd(d2)
23mpp3 3 gpio, ge0(txd2), lcd(d3)
24mpp4 4 gpio, ge0(txd3), lcd(d4)
25mpp5 5 gpio, ge0(txctl), lcd(d5)
26mpp6 6 gpio, ge0(rxd0), lcd(d6)
27mpp7 7 gpio, ge0(rxd1), lcd(d7)
28mpp8 8 gpio, ge0(rxd2), lcd(d8)
29mpp9 9 gpio, ge0(rxd3), lcd(d9)
30mpp10 10 gpio, ge0(rxctl), lcd(d10)
31mpp11 11 gpio, ge0(rxclk), lcd(d11)
32mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
33mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
34mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
35mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
36mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
37mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
38mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
39mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
40mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
41mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
42mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
43mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
44mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
45mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
46mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
47mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
48mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
49mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
50mpp30 30 gpio, tdm(int1), sd0(clk)
51mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
52mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
53mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
54mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
55mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
56mpp36 36 gpio, spi(mosi)
57mpp37 37 gpio, spi(miso)
58mpp38 38 gpio, spi(sck)
59mpp39 39 gpio, spi(cs0)
60mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
61 pcie(clkreq0)
62mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
63 pcie(clkreq1)
64mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
65 vdd(cpu0-pd)
66mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
67 vdd(cpu2-3-pd){1}
68mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
69 mem(bat)
70mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
71mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
72mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
73 ref(clkout)
74mpp48 48 gpio, tclk, dev(burst/last)
75
76* Marvell Armada XP (mv78260 and mv78460 only)
77
78name pins functions
79================================================================================
80mpp49 49 gpio, dev(we3)
81mpp50 50 gpio, dev(we2)
82mpp51 51 gpio, dev(ad16)
83mpp52 52 gpio, dev(ad17)
84mpp53 53 gpio, dev(ad18)
85mpp54 54 gpio, dev(ad19)
86mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
87mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
88mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
89mpp58 58 gpio, dev(ad23)
90mpp59 59 gpio, dev(ad24)
91mpp60 60 gpio, dev(ad25)
92mpp61 61 gpio, dev(ad26)
93mpp62 62 gpio, dev(ad27)
94mpp63 63 gpio, dev(ad28)
95mpp64 64 gpio, dev(ad29)
96mpp65 65 gpio, dev(ad30)
97mpp66 66 gpio, dev(ad31)
98
99Notes:
100* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
new file mode 100644
index 000000000000..a648aaad6110
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -0,0 +1,72 @@
1* Marvell Dove SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,dove-pinctrl"
8- clocks: (optional) phandle of pdma clock
9
10Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given
12only for more detailed description in this document.
13
14name pins functions
15================================================================================
16mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
17mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
18mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
19 uart1(rts)
20mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
21 uart1(cts), lcd-spi(cs1)
22mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
23mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
24mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
25mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
26mpp8 8 gpio, pmu, watchdog(rstout)
27mpp9 9 gpio, pmu, pex1(clkreq)
28mpp10 10 gpio, pmu, ssp(sclk)
29mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
30 sdio1(ledctrl), pex0(clkreq)
31mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
32mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
33 ssp(extclk)
34mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
35mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
36mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
37mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
38 ac97-1(sysclko)
39mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
40mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
41mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
42 ac97(sysclko)
43mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
44 uart1(cts), ssp(sfrm)
45mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
46 lcd-spi(mosi), uart1(cts), ssp(txd)
47mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
48 lcd-spi(sck), ssp(sclk)
49mpp_camera 24-39 gpio, camera
50mpp_sdio0 40-45 gpio, sdio0
51mpp_sdio1 46-51 gpio, sdio1
52mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
53 ssp/twsi
54mpp_spi0 58-61 gpio, spi0
55mpp_uart1 62-63 gpio, uart1
56mpp_nand 64-71 gpo, nand
57audio0 - i2s, ac97
58twsi - none, opt1, opt2, opt3
59
60Notes:
61* group "mpp_audio1" allows the following functions and gpio pins:
62 - gpio : gpio on pins 52-57
63 - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
64 - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
65 - spdifo : spdifo on pin 57, gpio on pins 52-55
66 - twsi : twsi on pins 56,57, gpio on pins 52-55
67 - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
68 - ssp : ssp on pins 52-55, gpio on pins 56,57
69 - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
70* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
71 audio0 pins.
72* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
new file mode 100644
index 000000000000..361bccb7ec89
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
1* Marvell Kirkwood SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10
11This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
12
13Available mpp pins/groups and functions:
14Note: brackets (x) are not part of the mpp name for marvell,function and given
15only for more detailed description in this document.
16
17* Marvell Kirkwood 88f6180
18
19name pins functions
20================================================================================
21mpp0 0 gpio, nand(io2), spi(cs)
22mpp1 1 gpo, nand(io3), spi(mosi)
23mpp2 2 gpo, nand(io4), spi(sck)
24mpp3 3 gpo, nand(io5), spi(miso)
25mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
26mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
27mpp6 6 sysrst(out), spi(mosi), ptp(trig)
28mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
29mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
30 mii(col)
31mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
32 mii(crs)
33mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
34mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
35 ptp-2(trig)
36mpp12 12 gpo, sdio(clk)
37mpp13 13 gpio, sdio(cmd), uart1(txd)
38mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
39mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
40mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
41mpp17 17 gpio, sdio(d3)
42mpp18 18 gpo, nand(io0)
43mpp19 19 gpo, nand(io1)
44mpp20 20 gpio, mii(rxerr)
45mpp21 21 gpio, audio(spdifi)
46mpp22 22 gpio, audio(spdifo)
47mpp23 23 gpio, audio(rmclk)
48mpp24 24 gpio, audio(bclk)
49mpp25 25 gpio, audio(sdo)
50mpp26 26 gpio, audio(lrclk)
51mpp27 27 gpio, audio(mclk)
52mpp28 28 gpio, audio(sdi)
53mpp29 29 gpio, audio(extclk)
54
55* Marvell Kirkwood 88f6190
56
57name pins functions
58================================================================================
59mpp0 0 gpio, nand(io2), spi(cs)
60mpp1 1 gpo, nand(io3), spi(mosi)
61mpp2 2 gpo, nand(io4), spi(sck)
62mpp3 3 gpo, nand(io5), spi(miso)
63mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
64mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
65mpp6 6 sysrst(out), spi(mosi), ptp(trig)
66mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
67mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
68 mii(col), mii-1(rxerr)
69mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
70 mii(crs), sata0(prsnt)
71mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
72mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
73 ptp-2(trig), sata0(act)
74mpp12 12 gpo, sdio(clk)
75mpp13 13 gpio, sdio(cmd), uart1(txd)
76mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
77mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
78mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
79mpp17 17 gpio, sdio(d3), sata0(prsnt)
80mpp18 18 gpo, nand(io0)
81mpp19 19 gpo, nand(io1)
82mpp20 20 gpio, ge1(txd0)
83mpp21 21 gpio, ge1(txd1), sata0(act)
84mpp22 22 gpio, ge1(txd2)
85mpp23 23 gpio, ge1(txd3), sata0(prsnt)
86mpp24 24 gpio, ge1(rxd0)
87mpp25 25 gpio, ge1(rxd1)
88mpp26 26 gpio, ge1(rxd2)
89mpp27 27 gpio, ge1(rxd3)
90mpp28 28 gpio, ge1(col)
91mpp29 29 gpio, ge1(txclk)
92mpp30 30 gpio, ge1(rxclk)
93mpp31 31 gpio, ge1(rxclk)
94mpp32 32 gpio, ge1(txclko)
95mpp33 33 gpo, ge1(txclk)
96mpp34 34 gpio, ge1(txen)
97mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
98
99* Marvell Kirkwood 88f6192
100
101name pins functions
102================================================================================
103mpp0 0 gpio, nand(io2), spi(cs)
104mpp1 1 gpo, nand(io3), spi(mosi)
105mpp2 2 gpo, nand(io4), spi(sck)
106mpp3 3 gpo, nand(io5), spi(miso)
107mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
108mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
109mpp6 6 sysrst(out), spi(mosi), ptp(trig)
110mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
111mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
112 mii(col), mii-1(rxerr), sata1(prsnt)
113mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
114 mii(crs), sata0(prsnt)
115mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
116mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
117 ptp-2(trig), sata0(act)
118mpp12 12 gpo, sdio(clk)
119mpp13 13 gpio, sdio(cmd), uart1(txd)
120mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
121mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
122mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
123 sata1(act)
124mpp17 17 gpio, sdio(d3), sata0(prsnt)
125mpp18 18 gpo, nand(io0)
126mpp19 19 gpo, nand(io1)
127mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
128 sata1(act)
129mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
130 audio(spdifo)
131mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
132 sata1(prsnt)
133mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
134 audio(bclk)
135mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
136mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
137mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
138mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
139mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
140mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
141mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
142mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
143mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
144mpp33 33 gpo, ge1(txclk), tdm(drx)
145mpp34 34 gpio, ge1(txen), tdm(spi-cs1)
146mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
147
148* Marvell Kirkwood 88f6281
149
150name pins functions
151================================================================================
152mpp0 0 gpio, nand(io2), spi(cs)
153mpp1 1 gpo, nand(io3), spi(mosi)
154mpp2 2 gpo, nand(io4), spi(sck)
155mpp3 3 gpo, nand(io5), spi(miso)
156mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
157mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
158mpp6 6 sysrst(out), spi(mosi), ptp(trig)
159mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
160mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
161 mii(col), mii-1(rxerr), sata1(prsnt)
162mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
163 mii(crs), sata0(prsnt)
164mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
165mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
166 ptp-2(trig), sata0(act)
167mpp12 12 gpio, sdio(clk)
168mpp13 13 gpio, sdio(cmd), uart1(txd)
169mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
170mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
171mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
172 sata1(act)
173mpp17 17 gpio, sdio(d3), sata0(prsnt)
174mpp18 18 gpo, nand(io0)
175mpp19 19 gpo, nand(io1)
176mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
177 sata1(act)
178mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
179 audio(spdifo)
180mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
181 sata1(prsnt)
182mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
183 audio(bclk)
184mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
185mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
186mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
187mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
188mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
189mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
190mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
191mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
192mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
193mpp33 33 gpo, ge1(txclk), tdm(drx)
194mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act)
195mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
196mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
197mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
198mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
199mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
200mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo)
201mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
202mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
203mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi)
204mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk)
205mpp45 45 gpio, ts(mp9), tdm(pclk)
206mpp46 46 gpio, ts(mp10), tdm(fs)
207mpp47 47 gpio, ts(mp11), tdm(drx)
208mpp48 48 gpio, ts(mp12), tdm(dtx)
209mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk)
210
211* Marvell Kirkwood 88f6282
212
213name pins functions
214================================================================================
215mpp0 0 gpio, nand(io2), spi(cs)
216mpp1 1 gpo, nand(io3), spi(mosi)
217mpp2 2 gpo, nand(io4), spi(sck)
218mpp3 3 gpo, nand(io5), spi(miso)
219mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
220mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
221mpp6 6 sysrst(out), spi(mosi)
222mpp7 7 gpo, spi(cs), lcd(pwm)
223mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
224 mii-1(rxerr), sata1(prsnt)
225mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
226 sata0(prsnt)
227mpp10 10 gpo, spi(sck), uart0(txd), sata1(act)
228mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act)
229mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
230mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
231mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
232 audio(spdifi), audio-1(sdi)
233mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
234 spi(cs)
235mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
236 sata1(act), lcd(extclk)
237mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
238mpp18 18 gpo, nand(io0), pex(clkreq)
239mpp19 19 gpo, nand(io1)
240mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
241 sata1(act), lcd(d0)
242mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
243 audio(spdifo), lcd(d1)
244mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
245 sata1(prsnt), lcd(d2)
246mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
247 audio(bclk), lcd(d3)
248mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
249 lcd(d4)
250mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
251 lcd(d5)
252mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
253 lcd(d6)
254mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
255 lcd(d7)
256mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
257 lcd(d8)
258mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
259mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
260mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
261mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
262mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13)
263mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
264mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
265 lcd(d15)
266mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
267mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
268mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
269mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
270mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
271mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
272mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
273mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
274mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
275mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e)
276mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
277mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
278mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
279mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 000000000000..0a26c3aa4e6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,46 @@
1* Marvell SoC pinctrl core driver for mpp
2
3The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
4(mpp) to a specific function. For each SoC family there is a SoC specific
5driver using this core driver.
6
7Please refer to pinctrl-bindings.txt in this directory for details of the
8common pinctrl bindings used by client devices, including the meaning of the
9phrase "pin configuration node".
10
11A Marvell SoC pin configuration node is a node of a group of pins which can
12be used for a specific device or function. Each node requires one or more
13mpp pins or group of pins and a mpp function common to all pins.
14
15Required properties for pinctrl driver:
16- compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
18
19Required properties for pin configuration node:
20- marvell,pins: string array of mpp pins or group of pins to be muxed.
21- marvell,function: string representing a function to mux to for all
22 marvell,pins given in this pin configuration node. The function has to be
23 common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
24 valid pin/pin group names and available function names for each SoC.
25
26Examples:
27
28uart1: serial@12100 {
29 compatible = "ns16550a";
30 reg = <0x12100 0x100>;
31 reg-shift = <2>;
32 interrupts = <7>;
33
34 pinctrl-0 = <&pmx_uart1_sw>;
35 pinctrl-names = "default";
36};
37
38pinctrl: pinctrl@d0200 {
39 compatible = "marvell,dove-pinctrl";
40 reg = <0xd0200 0x20>;
41
42 pmx_uart1_sw: pmx-uart1-sw {
43 marvell,pins = "mpp_uart1";
44 marvell,function = "uart1";
45 };
46};