diff options
author | Olof Johansson <olof@lixom.net> | 2013-04-03 02:06:48 -0400 |
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committer | Olof Johansson <olof@lixom.net> | 2013-04-03 02:06:57 -0400 |
commit | e382328a811fd6ffdb77ee16ff6a9e92e07561c5 (patch) | |
tree | 0f88d2b72d13842924570e1019e320e1e57d36b9 /Documentation | |
parent | 2f7053e0ecbe8908a130207bc01b7b3f9f854ef8 (diff) | |
parent | 202ac6a21a79500ef5aab4cd8665be2597e9345c (diff) |
Merge tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
* tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (185 commits)
sh-pfc: r8a73a4: Remove unused GPIO bias data
ARM: shmobile: r8a73a4: Remove all GPIO enums
sh-pfc: r8a73a4: Remove function GPIOs
ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
sh-pfc: r8a73a4: Remove IRQC function GPIOS
sh-pfc: r8a73a4: Remove SCIF function GPIOS
sh-pfc: r8a73a4: Add IRQC pin groups and functions
sh-pfc: r8a73a4: Add SCIF pin groups and functions
sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
sh-pfc: r8a73a4: GPIO IRQ support
sh-pfc: r8a73a4: Support sparse GPIO numbers
sh-pfc: Add r8a73a4 pinmux support
sh-pfc: r8a7779: Split DU input and output pixel clocks
sh-pfc: r8a7779: Remove GPIO data
ARM: shmobile: r8a7779: Register GPIO devices
sh-pfc: Configure pins as GPIOs at request time when handled externally
sh-pfc: Skip gpiochip registration when no GPIO resource is found
sh-pfc: Make GPIO support optional
sh-pfc: Make function GPIOs support optional
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/gpio/gpio.txt | 6 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt | 107 |
2 files changed, 109 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index a33628759d36..d933af370697 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt | |||
@@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example, | |||
98 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; | 98 | compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; |
99 | reg = <0x1460 0x18>; | 99 | reg = <0x1460 0x18>; |
100 | gpio-controller; | 100 | gpio-controller; |
101 | gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; | 101 | gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; |
102 | 102 | ||
103 | } | 103 | } |
104 | 104 | ||
@@ -107,8 +107,8 @@ where, | |||
107 | 107 | ||
108 | Next values specify the base pin and number of pins for the range | 108 | Next values specify the base pin and number of pins for the range |
109 | handled by 'qe_pio_e' gpio. In the given example from base pin 20 to | 109 | handled by 'qe_pio_e' gpio. In the given example from base pin 20 to |
110 | pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled | 110 | pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under |
111 | by this gpio controller. | 111 | pinctrl2 with gpio offset 10 is handled by this gpio controller. |
112 | 112 | ||
113 | The pinctrl node must have "#gpio-range-cells" property to show number of | 113 | The pinctrl node must have "#gpio-range-cells" property to show number of |
114 | arguments to pass with phandle from gpio controllers node. | 114 | arguments to pass with phandle from gpio controllers node. |
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 2c81e45f1374..fa1746b639b9 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt | |||
@@ -1,7 +1,9 @@ | |||
1 | One-register-per-pin type device tree based pinctrl driver | 1 | One-register-per-pin type device tree based pinctrl driver |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "pinctrl-single" | 4 | - compatible : "pinctrl-single" or "pinconf-single". |
5 | "pinctrl-single" means that pinconf isn't supported. | ||
6 | "pinconf-single" means that generic pinconf is supported. | ||
5 | 7 | ||
6 | - reg : offset and length of the register set for the mux registers | 8 | - reg : offset and length of the register set for the mux registers |
7 | 9 | ||
@@ -14,9 +16,61 @@ Optional properties: | |||
14 | - pinctrl-single,function-off : function off mode for disabled state if | 16 | - pinctrl-single,function-off : function off mode for disabled state if |
15 | available and same for all registers; if not specified, disabling of | 17 | available and same for all registers; if not specified, disabling of |
16 | pin functions is ignored | 18 | pin functions is ignored |
19 | |||
17 | - pinctrl-single,bit-per-mux : boolean to indicate that one register controls | 20 | - pinctrl-single,bit-per-mux : boolean to indicate that one register controls |
18 | more than one pin | 21 | more than one pin |
19 | 22 | ||
23 | - pinctrl-single,drive-strength : array of value that are used to configure | ||
24 | drive strength in the pinmux register. They're value of drive strength | ||
25 | current and drive strength mask. | ||
26 | |||
27 | /* drive strength current, mask */ | ||
28 | pinctrl-single,power-source = <0x30 0xf0>; | ||
29 | |||
30 | - pinctrl-single,bias-pullup : array of value that are used to configure the | ||
31 | input bias pullup in the pinmux register. | ||
32 | |||
33 | /* input, enabled pullup bits, disabled pullup bits, mask */ | ||
34 | pinctrl-single,bias-pullup = <0 1 0 1>; | ||
35 | |||
36 | - pinctrl-single,bias-pulldown : array of value that are used to configure the | ||
37 | input bias pulldown in the pinmux register. | ||
38 | |||
39 | /* input, enabled pulldown bits, disabled pulldown bits, mask */ | ||
40 | pinctrl-single,bias-pulldown = <2 2 0 2>; | ||
41 | |||
42 | * Two bits to control input bias pullup and pulldown: User should use | ||
43 | pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means | ||
44 | pullup, and the other one bit means pulldown. | ||
45 | * Three bits to control input bias enable, pullup and pulldown. User should | ||
46 | use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias | ||
47 | enable bit should be included in pullup or pulldown bits. | ||
48 | * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as | ||
49 | pinctrl-single,bias-disable. Because pinctrl single driver could implement | ||
50 | it by calling pulldown, pullup disabled. | ||
51 | |||
52 | - pinctrl-single,input-schmitt : array of value that are used to configure | ||
53 | input schmitt in the pinmux register. In some silicons, there're two input | ||
54 | schmitt value (rising-edge & falling-edge) in the pinmux register. | ||
55 | |||
56 | /* input schmitt value, mask */ | ||
57 | pinctrl-single,input-schmitt = <0x30 0x70>; | ||
58 | |||
59 | - pinctrl-single,input-schmitt-enable : array of value that are used to | ||
60 | configure input schmitt enable or disable in the pinmux register. | ||
61 | |||
62 | /* input, enable bits, disable bits, mask */ | ||
63 | pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; | ||
64 | |||
65 | - pinctrl-single,gpio-range : list of value that are used to configure a GPIO | ||
66 | range. They're value of subnode phandle, pin base in pinctrl device, pin | ||
67 | number in this range, GPIO function value of this GPIO range. | ||
68 | The number of parameters is depend on #pinctrl-single,gpio-range-cells | ||
69 | property. | ||
70 | |||
71 | /* pin base, nr pins & gpio function */ | ||
72 | pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>; | ||
73 | |||
20 | This driver assumes that there is only one register for each pin (unless the | 74 | This driver assumes that there is only one register for each pin (unless the |
21 | pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as | 75 | pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as |
22 | specified in the pinctrl-bindings.txt document in this directory. | 76 | specified in the pinctrl-bindings.txt document in this directory. |
@@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the | |||
42 | device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to | 96 | device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to |
43 | be used when applying this change to the register. | 97 | be used when applying this change to the register. |
44 | 98 | ||
99 | |||
100 | Optional sub-node: In case some pins could be configured as GPIO in the pinmux | ||
101 | register, those pins could be defined as a GPIO range. This sub-node is required | ||
102 | by pinctrl-single,gpio-range property. | ||
103 | |||
104 | Required properties in sub-node: | ||
105 | - #pinctrl-single,gpio-range-cells : the number of parameters after phandle in | ||
106 | pinctrl-single,gpio-range property. | ||
107 | |||
108 | range: gpio-range { | ||
109 | #pinctrl-single,gpio-range-cells = <3>; | ||
110 | }; | ||
111 | |||
112 | |||
45 | Example: | 113 | Example: |
46 | 114 | ||
47 | /* SoC common file */ | 115 | /* SoC common file */ |
@@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 { | |||
76 | pinctrl-single,function-mask = <0x5F>; | 144 | pinctrl-single,function-mask = <0x5F>; |
77 | }; | 145 | }; |
78 | 146 | ||
147 | /* third controller instance for pins in gpio domain */ | ||
148 | pmx_gpio: pinmux@d401e000 { | ||
149 | compatible = "pinconf-single"; | ||
150 | reg = <0xd401e000 0x0330>; | ||
151 | #address-cells = <1>; | ||
152 | #size-cells = <1>; | ||
153 | ranges; | ||
154 | |||
155 | pinctrl-single,register-width = <32>; | ||
156 | pinctrl-single,function-mask = <7>; | ||
157 | |||
158 | /* sparse GPIO range could be supported */ | ||
159 | pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 | ||
160 | &range 12 1 0 &range 13 29 1 | ||
161 | &range 43 1 0 &range 44 49 1 | ||
162 | &range 94 1 1 &range 96 2 1>; | ||
163 | |||
164 | range: gpio-range { | ||
165 | #pinctrl-single,gpio-range-cells = <3>; | ||
166 | }; | ||
167 | }; | ||
168 | |||
169 | |||
79 | /* board specific .dts file */ | 170 | /* board specific .dts file */ |
80 | 171 | ||
81 | &pmx_core { | 172 | &pmx_core { |
@@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 { | |||
96 | >; | 187 | >; |
97 | }; | 188 | }; |
98 | 189 | ||
190 | uart0_pins: pinmux_uart0_pins { | ||
191 | pinctrl-single,pins = < | ||
192 | 0x208 0 /* UART0_RXD (IOCFG138) */ | ||
193 | 0x20c 0 /* UART0_TXD (IOCFG139) */ | ||
194 | >; | ||
195 | pinctrl-single,bias-pulldown = <0 2 2>; | ||
196 | pinctrl-single,bias-pullup = <0 1 1>; | ||
197 | }; | ||
198 | |||
99 | /* map uart2 pins */ | 199 | /* map uart2 pins */ |
100 | uart2_pins: pinmux_uart2_pins { | 200 | uart2_pins: pinmux_uart2_pins { |
101 | pinctrl-single,pins = < | 201 | pinctrl-single,pins = < |
@@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 { | |||
122 | 222 | ||
123 | }; | 223 | }; |
124 | 224 | ||
225 | &uart1 { | ||
226 | pinctrl-names = "default"; | ||
227 | pinctrl-0 = <&uart0_pins>; | ||
228 | }; | ||
229 | |||
125 | &uart2 { | 230 | &uart2 { |
126 | pinctrl-names = "default"; | 231 | pinctrl-names = "default"; |
127 | pinctrl-0 = <&uart2_pins>; | 232 | pinctrl-0 = <&uart2_pins>; |