clk: sunxi: Rework MMC phase clocks

Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 8 insertions, 5 deletions

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 9dc4f55a04ad..e4c42276c577 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -55,8 +55,7 @@ Required properties:
         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
-        "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
-        "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
+        "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
         "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
         "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
         "allwinner,sun7i-a20-out-clk" - for the external output clocks
@@ -95,6 +94,10 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
 is the normal PLL6 output, or "pll6". The second output is rate doubled
 PLL6, or "pll6x2".
 
+The "allwinner,sun4i-a10-mmc-clk" has three different outputs: the
+main clock, with the ID 0, and the output and sample clocks, with the
+IDs 1 and 2, respectively.
+
 For example:
 
 osc24M: clk@01c20050 {
@@ -138,11 +141,11 @@ cpu: cpu@01c20054 {
 };
 
 mmc0_clk: clk@01c20088 {
-        #clock-cells = <0>;
-        compatible = "allwinner,sun4i-mod0-clk";
+        #clock-cells = <1>;
+        compatible = "allwinner,sun4i-a10-mmc-clk";
         reg = <0x01c20088 0x4>;
         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-        clock-output-names = "mmc0";
+        clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
 };
 
 mii_phy_tx_clk: clk@2 {