Merge tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc2

From Shawn Guo:
The imx soc changes for 3.10:

* Enable anatop, well bisa and RBC for suspend to optimize the power
  consumption a little bit
* Clock changes for TVE, LDB, PATA, SRTC support
* Add System Reset Controller (SRC) support for imx5 and imx6
* Add initial imx6dl support based on imx6q code
* Kconfig for cpufreq-cpu0, defconfig updates and few other changes

* tag 'imx-soc-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (275 commits)
  ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock
  ARM i.MX53: tve_di clock is not part of the CCM, but of TVE
  ARM i.MX53: make tve_ext_sel propagate rate change to PLL
  ARM i.MX53: Remove unused tve_gate clkdev entry
  ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree
  ARM: i.MX5: Add PATA and SRTC clocks
  ARM: imx: do not bring up unavailable cores
  ARM: imx: add initial imx6dl support
  ARM: imx1: mm: add call to mxc_device_init
  ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS
  ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS
  ARM: i.MX53 Add the cko1, cko2 clock outputs.
  staging: drm/imx: Use SRC to reset IPU
  ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)
  ARM: imx: do not use regmap_read for ANADIG_DIGPROG
  ARM i.MX6q: set the LDB serial clock parent to the video PLL
  ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1
  ARM i.MX6q: fix ldb di divider and selector clocks
  ARM i.MX53: fix ldb di divider and selector clocks
  ARM i.MX: Add imx_clk_divider_flags and imx_clk_mux_flags
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>

Trivial change/change conflict in arch/arm/mach-imx/mach-imx6q.c resolved.

6 files changed, 145 insertions, 4 deletions

diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 2a0c904c46ae..d71b4b2c077d 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -38,7 +38,6 @@ clocks and IDs.
         usb_phy_podf            23
         cpu_podf                24
         di_pred                 25
-        tve_di                  26
         tve_s                   27
         uart1_ipg_gate          28
         uart1_per_gate          29
@@ -172,6 +171,19 @@ clocks and IDs.
         can1_serial_gate        157
         can1_ipg_gate           158
         owire_gate              159
+        gpu3d_s                 160
+        gpu2d_s                 161
+        gpu3d_gate              162
+        gpu2d_gate              163
+        garb_gate               164
+        cko1_sel                165
+        cko1_podf               166
+        cko1                    167
+        cko2_sel                168
+        cko2_podf               169
+        cko2                    170
+        srtc_gate               171
+        pata_gate               172
 
 Examples (for mx53):
 
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 969b38e06ad3..6deb6fd1c7cd 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -205,6 +205,9 @@ clocks and IDs.
         enet_ref                190
         usbphy1_gate            191
         usbphy2_gate            192
+        pll4_post_div           193
+        pll5_post_div           194
+        pll5_video_div          195
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
new file mode 100644
index 000000000000..13301777e11c
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt
@@ -0,0 +1,49 @@
+Freescale i.MX System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "fsl,<chip>-src"
+- reg: should be register base and length as documented in the
+  datasheet
+- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
+  in this order.
+- #reset-cells: 1, see below
+
+example:
+
+src: src@020d8000 {
+        compatible = "fsl,imx6q-src";
+        reg = <0x020d8000 0x4000>;
+        interrupts = <0 91 0x04 0 96 0x04>;
+        #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+
+The system reset controller can be used to reset the GPU, VPU,
+IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
+nodes should specify the reset line on the SRC in their resets
+property, containing a phandle to the SRC device node and a
+RESET_INDEX specifying which module to reset, as described in
+reset.txt
+
+example:
+
+        ipu1: ipu@02400000 {
+                resets = <&src 2>;
+        };
+        ipu2: ipu@02800000 {
+                resets = <&src 4>;
+        };
+
+The following RESET_INDEX values are valid for i.MX5:
+GPU_RESET     0
+VPU_RESET     1
+IPU1_RESET    2
+OPEN_VG_RESET 3
+The following additional RESET_INDEX value is valid for i.MX6:
+IPU2_RESET    4
diff --git a/Documentation/devicetree/bindings/reset/reset.txt b/Documentation/devicetree/bindings/reset/reset.txt
new file mode 100644
index 000000000000..31db6ff84908
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/reset.txt
@@ -0,0 +1,75 @@
+= Reset Signal Device Tree Bindings =
+
+This binding is intended to represent the hardware reset signals present
+internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
+standalone chips are most likely better represented as GPIOs, although there
+are likely to be exceptions to this rule.
+
+Hardware blocks typically receive a reset signal. This signal is generated by
+a reset provider (e.g. power management or clock module) and received by a
+reset consumer (the module being reset, or a module managing when a sub-
+ordinate module is reset). This binding exists to represent the provider and
+consumer, and provide a way to couple the two together.
+
+A reset signal is represented by the phandle of the provider, plus a reset
+specifier - a list of DT cells that represents the reset signal within the
+provider. The length (number of cells) and semantics of the reset specifier
+are dictated by the binding of the reset provider, although common schemes
+are described below.
+
+A word on where to place reset signal consumers in device tree: It is possible
+in hardware for a reset signal to affect multiple logically separate HW blocks
+at once. In this case, it would be unwise to represent this reset signal in
+the DT node of each affected HW block, since if activated, an unrelated block
+may be reset. Instead, reset signals should be represented in the DT node
+where it makes most sense to control it; this may be a bus node if all
+children of the bus are affected by the reset signal, or an individual HW
+block node for dedicated reset signals. The intent of this binding is to give
+appropriate software access to the reset signals in order to manage the HW,
+rather than to slavishly enumerate the reset signal that affects each HW
+block.
+
+= Reset providers =
+
+Required properties:
+#reset-cells:   Number of cells in a reset specifier; Typically 0 for nodes
+                with a single reset output and 1 for nodes with multiple
+                reset outputs.
+
+For example:
+
+        rst: reset-controller {
+                #reset-cells = <1>;
+        };
+
+= Reset consumers =
+
+Required properties:
+resets:         List of phandle and reset specifier pairs, one pair
+                for each reset signal that affects the device, or that the
+                device manages. Note: if the reset provider specifies '0' for
+                #reset-cells, then only the phandle portion of the pair will
+                appear.
+
+Optional properties:
+reset-names:    List of reset signal name strings sorted in the same order as
+                the resets property. Consumers drivers will use reset-names to
+                match reset signal names with reset specifiers.
+
+For example:
+
+        device {
+                resets = <&rst 20>;
+                reset-names = "reset";
+        };
+
+This represents a device with a single reset signal named "reset".
+
+        bus {
+                resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
+                reset-names = "i2s1", "i2s2", "dma", "mixer";
+        };
+
+This represents a bus that controls the reset signal of each of four sub-
+ordinate devices. Consider for example a bus that fails to operate unless no
+child device has reset asserted.
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
index 07654f0338b6..f7698573cb9c 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
@@ -8,6 +8,8 @@ Required properties:
 - interrupts: Should contain sync interrupt and error interrupt,
   in this order.
 - #crtc-cells: 1, See below
+- resets: phandle pointing to the system reset controller and
+          reset line index, see reset/fsl,imx-src.txt for details
 
 example:
 
@@ -16,6 +18,7 @@ ipu: ipu@18000000 {
         compatible = "fsl,imx53-ipu";
         reg = <0x18000000 0x080000000>;
         interrupts = <11 10>;
+        resets = <&src 2>;
 };
 
 Parallel display support
diff --git a/Documentation/sound/alsa/ALSA-Configuration.txt b/Documentation/sound/alsa/ALSA-Configuration.txt
index 4499bd948860..95731a08f257 100644
--- a/Documentation/sound/alsa/ALSA-Configuration.txt
+++ b/Documentation/sound/alsa/ALSA-Configuration.txt
@@ -890,9 +890,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
     enable_msi  - Enable Message Signaled Interrupt (MSI) (default = off)
     power_save  - Automatic power-saving timeout (in second, 0 =
                 disable)
-    power_save_controller - Support runtime D3 of HD-audio controller
-                (-1 = on for supported chip (default), false = off,
-                 true = force to on even for unsupported hardware)
+    power_save_controller - Reset HD-audio controller in power-saving mode
+                (default = on)
     align_buffer_size - Force rounding of buffer/period sizes to multiples
                       of 128 bytes. This is more efficient in terms of memory
                       access but isn't required by the HDA spec and prevents