Merge branch 'clk-next' into v3.19-rc7

11 files changed, 198 insertions, 17 deletions

diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index 4ff84623d5e1..0e4f90aa1c13 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -73,6 +73,8 @@ the operations defined in clk.h:
                                                 unsigned long *parent_rate);
                 long            (*determine_rate)(struct clk_hw *hw,
                                                 unsigned long rate,
+                                                unsigned long min_rate,
+                                                unsigned long max_rate,
                                                 unsigned long *best_parent_rate,
                                                 struct clk_hw **best_parent_clk);
                 int             (*set_parent)(struct clk_hw *hw, u8 index);
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f80c1c3..6bf1e7493f61 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -34,6 +34,8 @@ Required Properties for Clock Controller:
         - "samsung,exynos7-clock-peris"
         - "samsung,exynos7-clock-fsys0"
         - "samsung,exynos7-clock-fsys1"
+        - "samsung,exynos7-clock-mscl"
+        - "samsung,exynos7-clock-aud"
 
  - reg: physical base address of the controller and the length of
         memory mapped region.
@@ -53,6 +55,7 @@ Input clocks for top0 clock controller:
         - dout_sclk_bus1_pll
         - dout_sclk_cc_pll
         - dout_sclk_mfc_pll
+        - dout_sclk_aud_pll
 
 Input clocks for top1 clock controller:
         - fin_pll
@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller:
         - sclk_uart1
         - sclk_uart2
         - sclk_uart3
+        - sclk_spi0
+        - sclk_spi1
+        - sclk_spi2
+        - sclk_spi3
+        - sclk_spi4
+        - sclk_i2s1
+        - sclk_pcm1
+        - sclk_spdif
 
 Input clocks for peris clock controller:
         - fin_pll
@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller:
         - dout_aclk_fsys1_200
         - dout_sclk_mmc0
         - dout_sclk_mmc1
+
+Input clocks for aud clock controller:
+        - fin_pll
+        - fout_aud_pll
diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.txt b/Documentation/devicetree/bindings/clock/qcom,lcc.txt
new file mode 100644
index 000000000000..dd755be63a01
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,lcc.txt
@@ -0,0 +1,21 @@
+Qualcomm LPASS Clock & Reset Controller Binding
+------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+                        "qcom,lcc-msm8960"
+                        "qcom,lcc-apq8064"
+                        "qcom,lcc-ipq8064"
+
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+- #reset-cells : shall contain 1
+
+Example:
+        clock-controller@28000000 {
+                compatible = "qcom,lcc-ipq8064";
+                reg = <0x28000000 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 266ff9d23229..df4a259a6898 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -1,6 +1,6 @@
-* Clock Block on Freescale CoreNet Platforms
+* Clock Block on Freescale QorIQ Platforms
 
-Freescale CoreNet chips take primary clocking input from the external
+Freescale qoriq chips take primary clocking input from the external
 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
 multiple phase locked loops (PLL) to create a variety of frequencies
 which can then be passed to a variety of internal logic, including
@@ -29,6 +29,7 @@ Required properties:
         * "fsl,t4240-clockgen"
         * "fsl,b4420-clockgen"
         * "fsl,b4860-clockgen"
+        * "fsl,ls1021a-clockgen"
         Chassis clock strings include:
         * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
         * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 2e18676bd4b5..0a80fa70ca26 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -11,6 +11,7 @@ Required Properties:
 
   - compatible: Must be one of the following
     - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
+    - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
     - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
     - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
new file mode 100644
index 000000000000..ece92393e80d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt
@@ -0,0 +1,33 @@
+* Renesas R8A73A4 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs
+and several fixed ratio dividers.
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a73a4-cpg-clocks"
+
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clocks ("extal1" and "extal2")
+
+  - #clock-cells: Must be 1
+
+  - clock-output-names: The names of the clocks. Supported clocks are "main",
+    "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
+    "m1", "m2", "zx", "zs", and "hp".
+
+
+Example
+-------
+
+        cpg_clocks: cpg_clocks@e6150000 {
+                compatible = "renesas,r8a73a4-cpg-clocks";
+                reg = <0 0xe6150000 0 0x10000>;
+                clocks = <&extal1_clk>, <&extal2_clk>;
+                #clock-cells = <1>;
+                clock-output-names = "main", "pll0", "pll1", "pll2",
+                                     "pll2s", "pll2h", "z", "z2",
+                                     "i", "m3", "b", "m1", "m2",
+                                     "zx", "zs", "hp";
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index e6ad35b894f9..b02944fba9de 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -8,15 +8,18 @@ Required Properties:
   - compatible: Must be one of
     - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
     - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
+    - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
     - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
     - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
 
   - reg: Base address and length of the memory resource used by the CPG
 
-  - clocks: Reference to the parent clock
+  - clocks: References to the parent clocks: first to the EXTAL clock, second
+    to the USB_EXTAL clock
   - #clock-cells: Must be 1
   - clock-output-names: The names of the clocks. Supported clocks are "main",
-    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
+    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
+    "adsp"
 
 
 Example
@@ -26,8 +29,9 @@ Example
                 compatible = "renesas,r8a7790-cpg-clocks",
                              "renesas,rcar-gen2-cpg-clocks";
                 reg = <0 0xe6150000 0 0x1000>;
-                clocks = <&extal_clk>;
+                clocks = <&extal_clk &usb_extal_clk>;
                 #clock-cells = <1>;
                 clock-output-names = "main", "pll0, "pll1", "pll3",
-                                     "lb", "qspi", "sdh", "sd0", "sd1", "z";
+                                     "lb", "qspi", "sdh", "sd0", "sd1", "z",
+                                     "rcan", "adsp";
         };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 67b2b99f2b33..60b44285250d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -26,7 +26,7 @@ Required properties:
         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
         "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
-        "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+        "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
         "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
@@ -55,9 +55,11 @@ Required properties:
         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
-        "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
-        "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
+        "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
+        "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
+        "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
         "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+        "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
         "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
         "allwinner,sun7i-a20-out-clk" - for the external output clocks
         "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
@@ -73,7 +75,9 @@ Required properties for all clocks:
 - #clock-cells : from common clock binding; shall be set to 0 except for
         the following compatibles where it shall be set to 1:
         "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
-        "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
+        "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
+        "allwinner,*-usb-clk", "allwinner,*-mmc-clk",
+        "allwinner,*-mmc-config-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
         If the clock module only has one output, the name shall be the
         module name.
@@ -81,6 +85,10 @@ Required properties for all clocks:
 And "allwinner,*-usb-clk" clocks also require:
 - reset-cells : shall be set to 1
 
+The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
+- #reset-cells : shall be set to 1
+- resets : shall be the reset control phandle for the mmc block.
+
 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
 
@@ -95,6 +103,14 @@ For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
 is the normal PLL6 output, or "pll6". The second output is rate doubled
 PLL6, or "pll6x2".
 
+The "allwinner,*-mmc-clk" clocks have three different outputs: the
+main clock, with the ID 0, and the output and sample clocks, with the
+IDs 1 and 2, respectively.
+
+The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
+per mmc controller. The number of outputs is determined by the size of
+the address block, which is related to the overall mmc block.
+
 For example:
 
 osc24M: clk@01c20050 {
@@ -138,11 +154,11 @@ cpu: cpu@01c20054 {
 };
 
 mmc0_clk: clk@01c20088 {
-        #clock-cells = <0>;
-        compatible = "allwinner,sun4i-mod0-clk";
+        #clock-cells = <1>;
+        compatible = "allwinner,sun4i-a10-mmc-clk";
         reg = <0x01c20088 0x4>;
         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
-        clock-output-names = "mmc0";
+        clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
 };
 
 mii_phy_tx_clk: clk@2 {
@@ -170,3 +186,16 @@ gmac_clk: clk@01c20164 {
         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
         clock-output-names = "gmac";
 };
+
+mmc_config_clk: clk@01c13000 {
+        compatible = "allwinner,sun9i-a80-mmc-config-clk";
+        reg = <0x01c13000 0x10>;
+        clocks = <&ahb0_gates 8>;
+        clock-names = "ahb";
+        resets = <&ahb0_resets 8>;
+        reset-names = "ahb";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        clock-output-names = "mmc0_config", "mmc1_config",
+                             "mmc2_config", "mmc3_config";
+};
diff --git a/Documentation/devicetree/bindings/clock/ti,cdce706.txt b/Documentation/devicetree/bindings/clock/ti,cdce706.txt
new file mode 100644
index 000000000000..616836e7e1e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti,cdce706.txt
@@ -0,0 +1,42 @@
+Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
+synthesizer/multiplier/divider.
+
+Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf
+
+I2C device node required properties:
+- compatible: shall be "ti,cdce706".
+- reg: i2c device address, shall be in range [0x68...0x6b].
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks: from common clock binding; list of parent clock
+  handles, shall be reference clock(s) connected to CLK_IN0
+  and CLK_IN1 pins.
+- clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
+  in case of crystal oscillator or differential signal input
+  configuration. Use clk_in0 and clk_in1 in case of independent
+  single-ended LVCMOS inputs configuration.
+
+Example:
+
+        clocks {
+                clk54: clk54 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <54000000>;
+                };
+        };
+        ...
+        i2c0: i2c-master@0d090000 {
+                ...
+                cdce706: clock-synth@69 {
+                        compatible = "ti,cdce706";
+                        #clock-cells = <1>;
+                        reg = <0x69>;
+                        clocks = <&clk54>;
+                        clock-names = "clk_in0";
+                };
+        };
+        ...
+        simple-audio-card,codec {
+                ...
+                clocks = <&cdce706 4>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/ti/fapll.txt b/Documentation/devicetree/bindings/clock/ti/fapll.txt
new file mode 100644
index 000000000000..c19b3f253b8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/fapll.txt
@@ -0,0 +1,33 @@
+Binding for Texas Instruments FAPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped FAPLL with usually two selectable input clocks
+(reference clock and bypass clock), and one or more child
+syntesizers.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "ti,dm816-fapll-clock"
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
+- reg : address and length of the register set for controlling the FAPLL.
+
+Examples:
+        main_fapll: main_fapll {
+                #clock-cells = <1>;
+                compatible = "ti,dm816-fapll-clock";
+                reg = <0x400 0x40>;
+                clocks = <&sys_clkin_ck &sys_clkin_ck>;
+                clock-indices = <1>, <2>, <3>, <4>, <5>,
+                                <6>, <7>;
+                clock-output-names = "main_pll_clk1",
+                                     "main_pll_clk2",
+                                     "main_pll_clk3",
+                                     "main_pll_clk4",
+                                     "main_pll_clk5",
+                                     "main_pll_clk6",
+                                     "main_pll_clk7";
+        };
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 91b3a3467150..4bf41d833804 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -10,8 +10,8 @@ Absolute maximum transfer rate is 200MB/s
 Required properties:
  - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"
  - reg : mmc controller base registers
- - clocks : a list with 2 phandle + clock specifier pairs
- - clock-names : must contain "ahb" and "mmc"
+ - clocks : a list with 4 phandle + clock specifier pairs
+ - clock-names : must contain "ahb", "mmc", "output" and "sample"
  - interrupts : mmc controller interrupt
 
 Optional properties:
@@ -25,8 +25,8 @@ Examples:
         mmc0: mmc@01c0f000 {
                 compatible = "allwinner,sun5i-a13-mmc";
                 reg = <0x01c0f000 0x1000>;
-                clocks = <&ahb_gates 8>, <&mmc0_clk>;
-                clock-names = "ahb", "mod";
+                clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>;
+                clock-names = "ahb", "mod", "output", "sample";
                 interrupts = <0 32 4>;
                 status = "disabled";
         };