dma: Add Freescale eDMA engine driver support

Add Freescale enhanced direct memory(eDMA) controller support.
This module can be found on Vybrid and LS-1 SoCs.

Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

1 files changed, 76 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt
new file mode 100644
index 000000000000..191d7bd8a6fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt
@@ -0,0 +1,76 @@
+* Freescale enhanced Direct Memory Access(eDMA) Controller
+
+  The eDMA channels have multiplex capability by programmble memory-mapped
+registers. channels are split into two groups, called DMAMUX0 and DMAMUX1,
+specific DMA request source can only be multiplexed by any channel of certain
+group, DMAMUX0 or DMAMUX1, but not both.
+
+* eDMA Controller
+Required properties:
+- compatible :
+        - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC
+- reg : Specifies base physical address(s) and size of the eDMA registers.
+        The 1st region is eDMA control register's address and size.
+        The 2nd and the 3rd regions are programmable channel multiplexing
+        control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+        interrupt-names.
+- interrupt-names : Should contain:
+        "edma-tx" - the transmission interrupt
+        "edma-err" - the error interrupt
+- #dma-cells : Must be <2>.
+        The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1).
+        Specific request source can only be multiplexed by specific channels
+        group called DMAMUX.
+        The 2nd cell specifies the request source(slot) ID.
+        See the SoC's reference manual for all the supported request sources.
+- dma-channels : Number of channels supported by the controller
+- clock-names : A list of channel group clock names. Should contain:
+        "dmamux0" - clock name of mux0 group
+        "dmamux1" - clock name of mux1 group
+- clocks : A list of phandle and clock-specifier pairs, one for each entry in
+        clock-names.
+
+Optional properties:
+- big-endian: If present registers and hardware scatter/gather descriptors
+        of the eDMA are implemented in big endian mode, otherwise in little
+        mode.
+
+
+Examples:
+
+edma0: dma-controller@40018000 {
+        #dma-cells = <2>;
+        compatible = "fsl,vf610-edma";
+        reg = <0x40018000 0x2000>,
+                <0x40024000 0x1000>,
+                <0x40025000 0x1000>;
+        interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
+                <0 9 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "edma-tx", "edma-err";
+        dma-channels = <32>;
+        clock-names = "dmamux0", "dmamux1";
+        clocks = <&clks VF610_CLK_DMAMUX0>,
+                <&clks VF610_CLK_DMAMUX1>;
+};
+
+
+* DMA clients
+DMA client drivers that uses the DMA function must use the format described
+in the dma.txt file, using a two-cell specifier for each channel: the 1st
+specifies the channel group(DMAMUX) in which this request can be multiplexed,
+and the 2nd specifies the request source.
+
+Examples:
+
+sai2: sai@40031000 {
+        compatible = "fsl,vf610-sai";
+        reg = <0x40031000 0x1000>;
+        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+        clock-names = "sai";
+        clocks = <&clks VF610_CLK_SAI2>;
+        dma-names = "tx", "rx";
+        dmas = <&edma0 0 21>,
+                <&edma0 0 20>;
+        status = "disabled";
+};