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authorHongbo Zhang <hongbo.zhang@freescale.com>2013-09-26 05:33:41 -0400
committerVinod Koul <vinod.koul@intel.com>2013-11-13 03:56:26 -0500
commitc3d68d8dd4f8d44579e2f0d121990f288c4a0e9a (patch)
tree98517dd66186e4e338614e42e4c40139c02cf381 /Documentation
parentc3cc74b2474fad7876e275b2aa30886d708e55c5 (diff)
DMA: Freescale: revise device tree binding document
This patch updates the discription of each type of DMA controller and its channels, it is preparation for adding another new DMA controller binding, it also fixes some defects of indent for text alignment at the same time. Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/dma.txt68
1 files changed, 31 insertions, 37 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
index 2a4b4bce6110..05841689c4a3 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
@@ -1,33 +1,30 @@
1* Freescale 83xx DMA Controller 1* Freescale DMA Controllers
2 2
3Freescale PowerPC 83xx have on chip general purpose DMA controllers. 3** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
5 series chips such as mpc8315, mpc8349, mpc8379 etc.
4 6
5Required properties: 7Required properties:
6 8
7- compatible : compatible list, contains 2 entries, first is 9- compatible : must include "fsl,elo-dma"
8 "fsl,CHIP-dma", where CHIP is the processor 10- reg : DMA General Status Register, i.e. DGSR which contains
9 (mpc8349, mpc8360, etc.) and the second is 11 status for all the 4 DMA channels
10 "fsl,elo-dma" 12- ranges : describes the mapping between the address space of the
11- reg : <registers mapping for DMA general status reg> 13 DMA channels and the address space of the DMA controller
12- ranges : Should be defined as specified in 1) to describe the
13 DMA controller channels.
14- cell-index : controller index. 0 for controller @ 0x8100 14- cell-index : controller index. 0 for controller @ 0x8100
15- interrupts : <interrupt mapping for DMA IRQ> 15- interrupts : interrupt specifier for DMA IRQ
16- interrupt-parent : optional, if needed for interrupt mapping 16- interrupt-parent : optional, if needed for interrupt mapping
17 17
18
19- DMA channel nodes: 18- DMA channel nodes:
20 - compatible : compatible list, contains 2 entries, first is 19 - compatible : must include "fsl,elo-dma-channel"
21 "fsl,CHIP-dma-channel", where CHIP is the processor 20 However, see note below.
22 (mpc8349, mpc8350, etc.) and the second is 21 - reg : DMA channel specific registers
23 "fsl,elo-dma-channel". However, see note below. 22 - cell-index : DMA channel index starts at 0.
24 - reg : <registers mapping for channel>
25 - cell-index : dma channel index starts at 0.
26 23
27Optional properties: 24Optional properties:
28 - interrupts : <interrupt mapping for DMA channel IRQ> 25 - interrupts : interrupt specifier for DMA channel IRQ
29 (on 83xx this is expected to be identical to 26 (on 83xx this is expected to be identical to
30 the interrupts property of the parent node) 27 the interrupts property of the parent node)
31 - interrupt-parent : optional, if needed for interrupt mapping 28 - interrupt-parent : optional, if needed for interrupt mapping
32 29
33Example: 30Example:
@@ -70,30 +67,27 @@ Example:
70 }; 67 };
71 }; 68 };
72 69
73* Freescale 85xx/86xx DMA Controller 70** Freescale EloPlus DMA Controller
74 71 This is a 4-channel DMA controller with extended addresses and chaining,
75Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. 72 mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
73 mpc8540, mpc8641 p4080, bsc9131 etc.
76 74
77Required properties: 75Required properties:
78 76
79- compatible : compatible list, contains 2 entries, first is 77- compatible : must include "fsl,eloplus-dma"
80 "fsl,CHIP-dma", where CHIP is the processor 78- reg : DMA General Status Register, i.e. DGSR which contains
81 (mpc8540, mpc8540, etc.) and the second is 79 status for all the 4 DMA channels
82 "fsl,eloplus-dma"
83- reg : <registers mapping for DMA general status reg>
84- cell-index : controller index. 0 for controller @ 0x21000, 80- cell-index : controller index. 0 for controller @ 0x21000,
85 1 for controller @ 0xc000 81 1 for controller @ 0xc000
86- ranges : Should be defined as specified in 1) to describe the 82- ranges : describes the mapping between the address space of the
87 DMA controller channels. 83 DMA channels and the address space of the DMA controller
88 84
89- DMA channel nodes: 85- DMA channel nodes:
90 - compatible : compatible list, contains 2 entries, first is 86 - compatible : must include "fsl,eloplus-dma-channel"
91 "fsl,CHIP-dma-channel", where CHIP is the processor 87 However, see note below.
92 (mpc8540, mpc8560, etc.) and the second is 88 - cell-index : DMA channel index starts at 0.
93 "fsl,eloplus-dma-channel". However, see note below. 89 - reg : DMA channel specific registers
94 - cell-index : dma channel index starts at 0. 90 - interrupts : interrupt specifier for DMA channel IRQ
95 - reg : <registers mapping for channel>
96 - interrupts : <interrupt mapping for DMA channel IRQ>
97 - interrupt-parent : optional, if needed for interrupt mapping 91 - interrupt-parent : optional, if needed for interrupt mapping
98 92
99Example: 93Example: