spi/rockchip: Add device tree property to configure Rx Sample Delay

We have found that we can sometimes see read failures on boards with
high-capacitance SPI lines. It seems that the controller samples the Rx
data line too early, and its register interface has an "Rx Sample Delay"
setting to fine-tune against this issue.

This patch adds a new optional device tree entry that can configure this
delay in terms of nanoseconds. The kernel will calculate the
best-fitting amount of parent clock ticks to program the controller with
based on that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>

1 files changed, 4 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 467dec441c62..0c491bda4c65 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -24,6 +24,9 @@ Optional Properties:
 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
                 Documentation/devicetree/bindings/dma/dma.txt
 - dma-names: DMA request names should include "tx" and "rx" if present.
+- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
+                Rx data (may need to be fine tuned for high capacitance lines).
+                No delay (0) by default.
 
 
 Example:
@@ -33,6 +36,7 @@ Example:
                 reg = <0xff110000 0x1000>;
                 dmas = <&pdma1 11>, <&pdma1 12>;
                 dma-names = "tx", "rx";
+                rx-sample-delay-ns = <10>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;