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authorOlof Johansson <olof@lixom.net>2013-02-05 16:19:03 -0500
committerOlof Johansson <olof@lixom.net>2013-02-05 16:19:03 -0500
commit0b6ad80abb1ad1584347e5ec5c5739ebc540a1a7 (patch)
treea91d4934ac4ffda651804b30554bb6da5af572d4 /Documentation
parentf015941f6b4a7d4d90c46a65bca17f2c2c41fb89 (diff)
parentf7c66dc0bf0f4ecd349c79315c87841c67e27aef (diff)
Merge branch 'next/soc' into next/dt
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/sirf.txt10
-rw-r--r--Documentation/devicetree/bindings/arm/vt8500.txt8
-rw-r--r--Documentation/devicetree/bindings/clock/imx31-clock.txt91
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt205
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt262
-rw-r--r--Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt3
-rw-r--r--Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt17
7 files changed, 594 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/arm/sirf.txt b/Documentation/devicetree/bindings/arm/sirf.txt
index 1881e1c6dda5..c6ba6d3c747f 100644
--- a/Documentation/devicetree/bindings/arm/sirf.txt
+++ b/Documentation/devicetree/bindings/arm/sirf.txt
@@ -1,3 +1,9 @@
1prima2 "cb" evaluation board 1CSR SiRFprimaII and SiRFmarco device tree bindings.
2========================================
3
2Required root node properties: 4Required root node properties:
3 - compatible = "sirf,prima2-cb", "sirf,prima2"; 5 - compatible:
6 - "sirf,prima2-cb" : prima2 "cb" evaluation board
7 - "sirf,marco-cb" : marco "cb" evaluation board
8 - "sirf,prima2" : prima2 device based board
9 - "sirf,marco" : marco device based board
diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt
index d657832c6819..87dc1ddf4770 100644
--- a/Documentation/devicetree/bindings/arm/vt8500.txt
+++ b/Documentation/devicetree/bindings/arm/vt8500.txt
@@ -12,3 +12,11 @@ compatible = "wm,wm8505";
12Boards with the Wondermedia WM8650 SoC shall have the following properties: 12Boards with the Wondermedia WM8650 SoC shall have the following properties:
13Required root node property: 13Required root node property:
14compatible = "wm,wm8650"; 14compatible = "wm,wm8650";
15
16Boards with the Wondermedia WM8750 SoC shall have the following properties:
17Required root node property:
18compatible = "wm,wm8750";
19
20Boards with the Wondermedia WM8850 SoC shall have the following properties:
21Required root node property:
22compatible = "wm,wm8850";
diff --git a/Documentation/devicetree/bindings/clock/imx31-clock.txt b/Documentation/devicetree/bindings/clock/imx31-clock.txt
new file mode 100644
index 000000000000..19df842c694f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx31-clock.txt
@@ -0,0 +1,91 @@
1* Clock bindings for Freescale i.MX31
2
3Required properties:
4- compatible: Should be "fsl,imx31-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX31
11clocks and IDs.
12
13 Clock ID
14 -----------------------
15 dummy 0
16 ckih 1
17 ckil 2
18 mpll 3
19 spll 4
20 upll 5
21 mcu_main 6
22 hsp 7
23 ahb 8
24 nfc 9
25 ipg 10
26 per_div 11
27 per 12
28 csi_sel 13
29 fir_sel 14
30 csi_div 15
31 usb_div_pre 16
32 usb_div_post 17
33 fir_div_pre 18
34 fir_div_post 19
35 sdhc1_gate 20
36 sdhc2_gate 21
37 gpt_gate 22
38 epit1_gate 23
39 epit2_gate 24
40 iim_gate 25
41 ata_gate 26
42 sdma_gate 27
43 cspi3_gate 28
44 rng_gate 29
45 uart1_gate 30
46 uart2_gate 31
47 ssi1_gate 32
48 i2c1_gate 33
49 i2c2_gate 34
50 i2c3_gate 35
51 hantro_gate 36
52 mstick1_gate 37
53 mstick2_gate 38
54 csi_gate 39
55 rtc_gate 40
56 wdog_gate 41
57 pwm_gate 42
58 sim_gate 43
59 ect_gate 44
60 usb_gate 45
61 kpp_gate 46
62 ipu_gate 47
63 uart3_gate 48
64 uart4_gate 49
65 uart5_gate 50
66 owire_gate 51
67 ssi2_gate 52
68 cspi1_gate 53
69 cspi2_gate 54
70 gacc_gate 55
71 emi_gate 56
72 rtic_gate 57
73 firi_gate 58
74
75Examples:
76
77clks: ccm@53f80000{
78 compatible = "fsl,imx31-ccm";
79 reg = <0x53f80000 0x4000>;
80 interrupts = <0 31 0x04 0 53 0x04>;
81 #clock-cells = <1>;
82};
83
84uart1: serial@43f90000 {
85 compatible = "fsl,imx31-uart", "fsl,imx21-uart";
86 reg = <0x43f90000 0x4000>;
87 interrupts = <45>;
88 clocks = <&clks 10>, <&clks 30>;
89 clock-names = "ipg", "per";
90 status = "disabled";
91};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
new file mode 100644
index 000000000000..0921fac73528
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -0,0 +1,205 @@
1NVIDIA Tegra20 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra20-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
16
17 The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 95 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
24
25 The balance of the clocks controlled by the CAR are assigned IDs of 96 and
26 above.
27
28 0 cpu
29 1 unassigned
30 2 unassigned
31 3 ac97
32 4 rtc
33 5 tmr
34 6 uart1
35 7 unassigned (register bit affects uart2 and vfir)
36 8 gpio
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 twc
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 ide
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 unassigned
59 31 cache2
60
61 32 mem
62 33 ahbdma
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 stat_mon
67 38 pmc
68 39 fuse
69 40 kfuse
70 41 sbc1
71 42 snor
72 43 spi1
73 44 sbc2
74 45 xio
75 46 sbc3
76 47 dvc
77 48 dsi
78 49 unassigned (register bit affects tvo and cve)
79 50 mipi
80 51 hdmi
81 52 csi
82 53 tvdac
83 54 i2c2
84 55 uart3
85 56 unassigned
86 57 emc
87 58 usb2
88 59 usb3
89 60 mpe
90 61 vde
91 62 bsea
92 63 bsev
93
94 64 speedo
95 65 uart4
96 66 uart5
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 pcie
101 71 owr
102 72 afi
103 73 csite
104 74 unassigned
105 75 avpucq
106 76 la
107 77 unassigned
108 78 unassigned
109 79 unassigned
110 80 unassigned
111 81 unassigned
112 82 unassigned
113 83 unassigned
114 84 irama
115 85 iramb
116 86 iramc
117 87 iramd
118 88 cram2
119 89 audio_2x a/k/a audio_2x_sync_clk
120 90 clk_d
121 91 unassigned
122 92 sus
123 93 cdev1
124 94 cdev2
125 95 unassigned
126
127 96 uart2
128 97 vfir
129 98 spdif_in
130 99 spdif_out
131 100 vi
132 101 vi_sensor
133 102 tvo
134 103 cve
135 104 osc
136 105 clk_32k a/k/a clk_s
137 106 clk_m
138 107 sclk
139 108 cclk
140 109 hclk
141 110 pclk
142 111 blink
143 112 pll_a
144 113 pll_a_out0
145 114 pll_c
146 115 pll_c_out1
147 116 pll_d
148 117 pll_d_out0
149 118 pll_e
150 119 pll_m
151 120 pll_m_out1
152 121 pll_p
153 122 pll_p_out1
154 123 pll_p_out2
155 124 pll_p_out3
156 125 pll_p_out4
157 126 pll_s
158 127 pll_u
159 128 pll_x
160 129 cop a/k/a avp
161 130 audio a/k/a audio_sync_clk
162 131 pll_ref
163 132 twd
164
165Example SoC include file:
166
167/ {
168 tegra_car: clock {
169 compatible = "nvidia,tegra20-car";
170 reg = <0x60006000 0x1000>;
171 #clock-cells = <1>;
172 };
173
174 usb@c5004000 {
175 clocks = <&tegra_car 58>; /* usb2 */
176 };
177};
178
179Example board file:
180
181/ {
182 clocks {
183 compatible = "simple-bus";
184 #address-cells = <1>;
185 #size-cells = <0>;
186
187 osc: clock@0 {
188 compatible = "fixed-clock";
189 reg = <0>;
190 #clock-cells = <0>;
191 clock-frequency = <12000000>;
192 };
193
194 clk_32k: clock@1 {
195 compatible = "fixed-clock";
196 reg = <1>;
197 #clock-cells = <0>;
198 clock-frequency = <32768>;
199 };
200 };
201
202 &tegra_car {
203 clocks = <&clk_32k> <&osc>;
204 };
205};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
new file mode 100644
index 000000000000..f3da3be5fcad
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -0,0 +1,262 @@
1NVIDIA Tegra30 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra30-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
16
17 The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 160 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
24
25 The balance of the clocks controlled by the CAR are assigned IDs of 160 and
26 above.
27
28 0 cpu
29 1 unassigned
30 2 unassigned
31 3 unassigned
32 4 rtc
33 5 timer
34 6 uarta
35 7 unassigned (register bit affects uartb and vfir)
36 8 gpio
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 unassigned
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 unassigned
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 i2s0
59 31 cop_cache
60
61 32 mc
62 33 ahbdma
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 statmon
67 38 pmc
68 39 unassigned (register bit affects fuse and fuse_burn)
69 40 kfuse
70 41 sbc1
71 42 nor
72 43 unassigned
73 44 sbc2
74 45 unassigned
75 46 sbc3
76 47 i2c5
77 48 dsia
78 49 unassigned (register bit affects cve and tvo)
79 50 mipi
80 51 hdmi
81 52 csi
82 53 tvdac
83 54 i2c2
84 55 uartc
85 56 unassigned
86 57 emc
87 58 usb2
88 59 usb3
89 60 mpe
90 61 vde
91 62 bsea
92 63 bsev
93
94 64 speedo
95 65 uartd
96 66 uarte
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 pcie
101 71 owr
102 72 afi
103 73 csite
104 74 pciex
105 75 avpucq
106 76 la
107 77 unassigned
108 78 unassigned
109 79 dtv
110 80 ndspeed
111 81 i2cslow
112 82 dsib
113 83 unassigned
114 84 irama
115 85 iramb
116 86 iramc
117 87 iramd
118 88 cram2
119 89 unassigned
120 90 audio_2x a/k/a audio_2x_sync_clk
121 91 unassigned
122 92 csus
123 93 cdev2
124 94 cdev1
125 95 unassigned
126
127 96 cpu_g
128 97 cpu_lp
129 98 3d2
130 99 mselect
131 100 tsensor
132 101 i2s3
133 102 i2s4
134 103 i2c4
135 104 sbc5
136 105 sbc6
137 106 d_audio
138 107 apbif
139 108 dam0
140 109 dam1
141 110 dam2
142 111 hda2codec_2x
143 112 atomics
144 113 audio0_2x
145 114 audio1_2x
146 115 audio2_2x
147 116 audio3_2x
148 117 audio4_2x
149 118 audio5_2x
150 119 actmon
151 120 extern1
152 121 extern2
153 122 extern3
154 123 sata_oob
155 124 sata
156 125 hda
157 127 se
158 128 hda2hdmi
159 129 sata_cold
160
161 160 uartb
162 161 vfir
163 162 spdif_in
164 163 spdif_out
165 164 vi
166 165 vi_sensor
167 166 fuse
168 167 fuse_burn
169 168 cve
170 169 tvo
171
172 170 clk_32k
173 171 clk_m
174 172 clk_m_div2
175 173 clk_m_div4
176 174 pll_ref
177 175 pll_c
178 176 pll_c_out1
179 177 pll_m
180 178 pll_m_out1
181 179 pll_p
182 180 pll_p_out1
183 181 pll_p_out2
184 182 pll_p_out3
185 183 pll_p_out4
186 184 pll_a
187 185 pll_a_out0
188 186 pll_d
189 187 pll_d_out0
190 188 pll_d2
191 189 pll_d2_out0
192 190 pll_u
193 191 pll_x
194 192 pll_x_out0
195 193 pll_e
196 194 spdif_in_sync
197 195 i2s0_sync
198 196 i2s1_sync
199 197 i2s2_sync
200 198 i2s3_sync
201 199 i2s4_sync
202 200 vimclk
203 201 audio0
204 202 audio1
205 203 audio2
206 204 audio3
207 205 audio4
208 206 audio5
209 207 clk_out_1 (extern1)
210 208 clk_out_2 (extern2)
211 209 clk_out_3 (extern3)
212 210 sclk
213 211 blink
214 212 cclk_g
215 213 cclk_lp
216 214 twd
217 215 cml0
218 216 cml1
219 217 hclk
220 218 pclk
221
222Example SoC include file:
223
224/ {
225 tegra_car: clock {
226 compatible = "nvidia,tegra30-car";
227 reg = <0x60006000 0x1000>;
228 #clock-cells = <1>;
229 };
230
231 usb@c5004000 {
232 clocks = <&tegra_car 58>; /* usb2 */
233 };
234};
235
236Example board file:
237
238/ {
239 clocks {
240 compatible = "simple-bus";
241 #address-cells = <1>;
242 #size-cells = <0>;
243
244 osc: clock@0 {
245 compatible = "fixed-clock";
246 reg = <0>;
247 #clock-cells = <0>;
248 clock-frequency = <12000000>;
249 };
250
251 clk_32k: clock@1 {
252 compatible = "fixed-clock";
253 reg = <1>;
254 #clock-cells = <0>;
255 clock-frequency = <32768>;
256 };
257 };
258
259 &tegra_car {
260 clocks = <&clk_32k> <&osc>;
261 };
262};
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index e9b005dc7625..34c952883276 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -11,6 +11,7 @@ Required properties :
11 - phy_type : Should be one of "ulpi" or "utmi". 11 - phy_type : Should be one of "ulpi" or "utmi".
12 - nvidia,vbus-gpio : If present, specifies a gpio that needs to be 12 - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
13 activated for the bus to be powered. 13 activated for the bus to be powered.
14 - nvidia,phy : phandle of the PHY instance, the controller is connected to.
14 15
15Required properties for phy_type == ulpi: 16Required properties for phy_type == ulpi:
16 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. 17 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
@@ -27,3 +28,5 @@ Optional properties:
27 registers are accessed through the APB_MISC base address instead of 28 registers are accessed through the APB_MISC base address instead of
28 the USB controller. Since this is a legacy issue it probably does not 29 the USB controller. Since this is a legacy issue it probably does not
29 warrant a compatible string of its own. 30 warrant a compatible string of its own.
31 - nvidia,needs-double-reset : boolean is to be set for some of the Tegra2
32 USB ports, which need reset twice due to hardware issues.
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
new file mode 100644
index 000000000000..6bdaba2f0aa1
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -0,0 +1,17 @@
1Tegra SOC USB PHY
2
3The device node for Tegra SOC USB PHY:
4
5Required properties :
6 - compatible : Should be "nvidia,tegra20-usb-phy".
7 - reg : Address and length of the register set for the USB PHY interface.
8 - phy_type : Should be one of "ulpi" or "utmi".
9
10Required properties for phy_type == ulpi:
11 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
12
13Optional properties:
14 - nvidia,has-legacy-mode : boolean indicates whether this controller can
15 operate in legacy mode (as APX 2500 / 2600). In legacy mode some
16 registers are accessed through the APB_MISC base address instead of
17 the USB controller. \ No newline at end of file
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 20:44:32 -0500