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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-12-20 17:30:42 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-12-20 17:30:42 -0500
commit2593f939a5fa7564ba5be0fd5aec4bb1162bd4b2 (patch)
treee605e977dfb7a03b89ee85ffb643e8645a6752ac /Documentation
parent698cd335a782561b79504d4e98c7df62b08e7abd (diff)
parentc1a676dfa2fa25fb9ec77c92ebe3ff580648b6ac (diff)
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1* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
2
3The OpenPIC specification does not specify which interrupt source has to
4become which interrupt number. This is up to the software implementation
5of the interrupt controller. The only requirement is that every
6interrupt source has to have an unique interrupt number / vector number.
7To accomplish this the current implementation assigns the number zero to
8the first source, the number one to the second source and so on until
9all interrupt sources have their unique number.
10Usually the assigned vector number equals the interrupt number mentioned
11in the documentation for a given core / CPU. This is however not true
12for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
13between internal and external interrupt sources and starts counting at
14zero for both of them.
15
16So what to write for external interrupt source X or internal interrupt
17source Y into the device tree? Here is an example:
18
19The memory map for the interrupt controller in the MPC8544[0] shows,
20that the first interrupt source starts at 0x5_0000 (PIC Register Address
21Map-Interrupt Source Configuration Registers). This source becomes the
22number zero therefore:
23 External interrupt 0 = interrupt number 0
24 External interrupt 1 = interrupt number 1
25 External interrupt 2 = interrupt number 2
26 ...
27Every interrupt number allocates 0x20 bytes register space. So to get
28its number it is sufficient to shift the lower 16bits to right by five.
29So for the external interrupt 10 we have:
30 0x0140 >> 5 = 10
31
32After the external sources, the internal sources follow. The in core I2C
33controller on the MPC8544 for instance has the internal source number
3427. Oo obtain its interrupt number we take the lower 16bits of its memory
35address (0x5_0560) and shift it right:
36 0x0560 >> 5 = 43
37
38Therefore the I2C device node for the MPC8544 CPU has to have the
39interrupt number 43 specified in the device tree.
40
41[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
42 MPC8544ERM Rev. 1 10/2007